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| Programmable Peripheral PSD3XX Family Field-Programmable Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t Wide Operating Voltage Range -- L-Versions: 3.0 to 5.5 volts -- Others: 4.5 to 5.5 volts t 19 Individually Configurable I/O pins that can be used as -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A and PAD B) -- Total of 40 Product Terms and up to 16 Inputs and 24 Outputs -- Address Decoding up to 1 MB -- Logic replacement of discrete PALs (R) t "No Glue" Microcontroller Chip-Set -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode ALE and Reset (non-PSD3XXL versions) polarity programmable Selectable modes for read and write control bus as RD/WR or R/W/E t 256K to 2 MBits of UV EPROM (2 Mbit version is SRAMless) -- -- -- -- Configurable as 32, 64, 128 or 256K x 8 or as 16, 32, 64 or 128K x 16 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 4K x 8 or 2K x 16 (PSD3X1) to 32K x 8 or 16K x 16 (PSD3X4R) As fast as 70 ns EPROM access time, including input latches and PAD address decoding. t 16 Kbit Static RAM (No SRAM on PSD3XXR versions) -- Configurable as 2K x 8 or as 1K x 16 -- As fast as 70 ns SRAM access time, including input latches and PAD address decoding t Built-in Page Logic (PSD3X2/3X3/3X4R) -- Expands the MCU address space up to sixteen 1 Mb pages t CMiser Bit -- Programmable option to further reduce power consumption t Address/Data Track Mode -- Enables easy Interface to Shared Resources (Mail Box SRAM) with other Microcontrollers or a Host Processor t Built-In Security -- Locks the device and PAD Decoding configuration 2-1 PSD3XX Family Key Features (Cont.) t Available in a Variety of Packaging -- 44 Pin PLDCC, CLDCC, PQFP, TQFP, and CPGA t Simple Menu-Driven Software: Configure the PSD3XX on an IBM PC t PSD3XX standard versions are excellent for general purpose applications t PSD3XXR SRAMless versions result in lower cost t PSD3XXL versions (3.0 to 5.5 volt operation) eliminate mixing and matching discrete low-voltage parts t PSD3XXM mask-programmable versions are ideal for code-stable, high-volume low cost applications PSD3XX Family Feature Summary Part PSD301(R) PSD311 PSD302 PSD312 PSD303 PSD313 PSD304R PSD314R PLD Inputs/ EPROM SRAM Memory C-Miser Security Ports Configuration Product Size Size Paging Bit Bit Terms 14/40 14/40 18/40 18/40 18/40 18/40 18/40 18/40 19 19 19 19 19 19 19 19 256 Kb 256 Kb 512 Kb 512 Kb 1 Mb 1 Mb 2 Mb 2 Mb 16 Kb 16 Kb 16 Kb 16 Kb 16 Kb 16 Kb - - x8 or x16 x8 x8 or x16 x8 x8 or x16 x8 x8 or x16 x8 X X X X X X X X X X X X X X X X X X X X X X Partial Listing of Microcontrollers Supported t Motorola family: M6805, M68HC11, M68HC16, M68000/10/20, M60008, M683XX t Intel family: 8031/8051, 8096/8098, 80186/88, 80196/98 t Philips Semiconductors: SC80C451, SC80552 t TI: SC80C451, TMS320C14 t Zilog: Z8, Z80, Z180 t National: HPC16000, HPC46400 t Echelon: NEURON (R) 3150TM Chip Applications t Computers (Notebook and Portable PCs) -- Fixed Disk Control, Modem, Imaging, Laser Printer Control t Telecommunications -- Modem, Cellular Phone, Digital PBX, Digital Speech, FAX, Digital Signal Processing t Portable Industrial Equipment -- Measurement Instruments, Data Recorders t Medical Instrumentation -- Monitoring Equipment, Diagnostic Tools 2-2 PSD3XX Family Introduction The PSD3XX family is the market's first single-chip solution for microcontroller-based applications where criteria such as fast time-to-market, small form factor, and low power consumption are essential. When combined in an 8- or 16-bit system, virtually any microcontroller (68HC11, 8031/8051, 80186, etc.) and the PSD3XX device work together to create a very powerful chip-set solution. The low-voltage PSD3XXL versions eliminate mixing and matching low voltage specifications for various discrete components. They also provide all the required control and peripheral elements needed in a microcontroller-based system with no external discrete "glue" logic required. The PSD3XX family comes complete with simple system software development tools for interfacing the PSD3XX with a microcontroller. Hosted on an IBM PC platform or compatible, the easy to use PSDsoft software enables the designer to quickly configure the device and use it immediately. PSD3XX standard versions are ideal for general purpose embedded control applications. PSD3XXR (SRAM-less) versions are optimized for designs that either require no on-chip SRAM or require large off-chip SRAMs for data storage. (SRAM-less versions were formerly identified by a "C1" suffix to the part number.) PSD3XXM mask-programmable versions deliver the lowest cost PSD3XX solution. See the Masked-PSD Ordering Information chapter in this databook for the mask-programmable PSD3XXM ordering procedure. PSD3XXL low-power versions operate down to 3.0 volts and feature standby current of only 1 A typical. Combinations of the above versions are available. See the ordering information section at the end of this data sheet. References in this document to PSD3XX versions include any "Non-L" products (e.g., PSD3XX, PSD3XXR, PSD3XXM and PSD3XXRM). References to PSD3XXR include any SRAM-less product (PSD3XXR, PSD3XXRM, PSD3XXRL and PSD3XXRLM). References to PSD3XXM include PSD3XXM, PSD3XXRM, PSD3XXLM, and PSD3XXRLM products. References to PSD3XXL include PSD3XXL, PSD3XXLM, PSD3XXRL and PSD3XXRLM products. Revisions Product Revisions Original PSD3XX Revision A PSD3XX-A Revision Reason Initial release Design changed for improved manufacturability and improved margin to specification. Data Sheet Changes - None See page 1-15 for general description of product numbering. PSD301 is a registered trademark of WaferScale Integration, Inc. PAL is a registered trademark of Advanced Micro Devices, Inc. 2-3 PSD3XX Family Product Description The PSD3XX family integrates high performance user-configurable blocks of EPROM, SRAM, and programmable logic. The major functional blocks include two programmable logic arrays, PAD A and PAD B, 256K to 2Mbit of EPROM, 16K bits of SRAM (no SRAM on PSD3XXR versions), input latches, and output ports. The PSD3XX family is ideal for applications requiring low power and very small form factors. These include hard disk control, modems, cellular telephones, instrumentation, computer peripherals, military and similar applications. The PSD3XX family offers a unique single-chip solution for microcontrollers that need: t I/O reconstruction (microcontrollers lose at least two I/O ports when accessing external resources). t More EPROM and SRAM than the microcontroller's internal memory. t 3.3 volt system operation (PSD3XXL versions). t Chip-select, control, or latched address lines that are otherwise implemented discretely. t An interface to shared external resources. t Expanded microcontroller address space. WSI's PSD3XX Family Architecture (Figure 1) can efficiently interface with, and enhance, any low-voltage 8- or 16-bit microcontroller system. This is the first solution that provides microcontrollers with port expansion, latched addresses, page logic, two programmable logic arrays (PAD A and PAD B), an interface to shared resources, 256K, 512K, 1M, or 2Mbit EPROM, and 16K bit SRAM on a single chip. The PSD3XX family does not require any glue logic for interfacing to any 8- or 16-bit microcontroller. The 8051 microcontroller family can take full advantage of the PSD3XX's separate program and data address spaces. Users of the 68HCXX microcontroller family can change the functionality of the control signals and directly connect the R/W and E, or the R/W and DS signals. (Users of 16-bit microcontrollers, including the 80186, 8096, 80196 and 16XXX, can use the PSD301/302/303 in a 16-bit configuration). Address and data buses can be configured as separate or multiplexed, whichever is required by the host processor. The flexibility of the PSD3XX I/O ports permits interfacing to shared resources. The arbitration can be controlled internally by PAD A outputs. The user can assign the following functions to these ports: standard I/O pins, chip-select outputs from PAD A and PAD B, or latched address or multiplexed low-order address/data byte. This enables users to design add-on systems such as disk drives, modems, etc., that easily interface to the host bus (e.g., IBM PC, SCSI). The page register extends the accessible address space of certain microcontrollers from 64 K to 1 M. There are 16 pages that can serve as base address inputs to the PAD, thereby enlarging the address space of 16 address line microcontrollers by a factor of 16. 2-4 PSD3XX Family Figure 1. PSD3XX Family Architecture AD8-AD15 L A T C H A11-A15 A8-A10 A19/CSI ALE/AS RD WR ALE/AS RESET PAGE LOGIC* P3-P0 A16-A18 PROG. PORT EXP. PC0- PC2 CSIOPORT A19/CSI PAD A ALE/AS RD 13 P.T. WR RESET LOGIC IN PAD B CS8- CS10 PORT C 27 P.T. AD0-AD7 L A T C H ES7 ES6 ES5 ES4 ES3 ES2 ES1 ES0 16/8 MUX D8-D15 EPROM 256Kb TO 2Mb CS0- CS7 PROG. PORT EXP. PB0- PB7 PORT B D8-D15 CSIOPORT D0-D7 RS0 SRAM 16K BIT ** A0-A7 AD0-AD7/D0-D7 ALE/AS RD/E/DS WR/R/W BHE/PSEN RESET A19/CSI PROG. CONTROL SIGNALS PROG. CHIP CONFIGURATION TRACK MODE SELECTS PROG. PORT EXP. PA0- PA7 PORT A X8, X16 MUX or NON-MUX BUSSES SECURITY MODE **PSD3X2/3X3/3X4R only. **Not available on PSD3XXR versions. 2-5 PSD3XX Family Table 1. PSD3XX Pin Descriptions Name Type Description When the data bus width is 8 bits (CDATA = 0), this pin is PSEN. In this mode, PSEN is the active low EPROM read pulse. The SRAM and I/O ports read signal is generated according to the description of the WR/VPP or R/W and RD/E/DS pins. If the host processor is a member of the 8031 family, PSEN must be connected to the corresponding host pin. In other 8-bit host processors that do not have a special EPROM-only read strobe, PSEN should be tied to VCC. In this case, RD or E and R/W provide the read strobe for the SRAM, I/O ports, and EPROM. When the data bus width is configured as 16 (CDATA = 1), this pin is BHE. When BHE is low, data bus bits D8-D15 are read from, or written into, the PSD3XX, depending on the operation being read or write, respectively. In programming mode, this pin is pulsed between VPP and 0. The PSEN is the active low EPROM read pulse. The SRAM and I/O ports read signal is generated according to the description of the WR/VPP or R/W, and RD/E pins. If the host processor is a member of the 8031 family, PSEN must be connected to the correspondinbg host pin. In other 8-bit host processors that do not have a special EPROM-only read strobe, PSEN should be tied to VCC. In this case, RD or E and R/W provide the read strobe for the SRAM, I/O ports, and EPROM. In the operating mode this pin's function is WR (CRRWR = 0) or R/W (CRRWR = 1). When configured as R/W, the following tables summarize the read and write operations (CRRWR = 1): BHE/PSEN (PSD30X Devices) I or PSEN (PSD31X Devices Only) I WR/VPP or R/W/VPP I CEDS = 0 R/W E X 0 NOP 0 1 write 1 1 read CEDS = 1 (Note 2) R/W DS X 1 NOP 0 0 write 1 0 read When configured as WR, a write operation is executed during an active low pulse. When configured as R/W, with R/W = 1 and E = 1, a read operation is executed; if R/W = 0 and E = 1, a write operation is executed. In programming mode, this pin must be tied to VPP voltage. The pin function depends on the CRRWR and CEDS configuration bits. If CRRWR = 0, RD is an active low read pulse. When CRRWR = 1, this pin and the R/W pin define the following cycle type: If CEDS = 0, E is an active high strobe. If CEDS = 1, DS is an active low strobe. When configured as RD (CRRWR = 0), this pin provides an active low RD strobe. When configured as E (CRRWR = 1), this pin becomes an active high pulse, which, together with R/W defines the cycle type. Then, if R/W = 1 and E = 1, a read operation is executed. If R/W = 0 and E = 1, a write operation is executed. RD/E/DS (Note 2) or RD/E (Note 3) I I Legend: The I/O column abbreviations are: I = input; I/O = input/output; P = power. NOTE: 1. All the configuration bits mentioned in Table 1 appear in parentheses and are explained in the Configuration Register section. 2. PSD3X2/3X3/3X4R only. 3. PSD3X1 only. 2-6 PSD3XX Family Table 1. PSD3XX Pin Descriptions (Cont.) Name Type Description This pin has two configurations. When it is CSI (A19/CSI = 0) and the pin is asserted high, the device is deselected and powered down. (See Tables 12 and 13 for the chip state during power-down mode.) If the pin is asserted low, the chip is in normal operational mode. When it is configured as A19, (A19/CSI = 1), this pin can be used as an additional input to the PAD. CADLOG3 = 1 (CATD = 1 for PSD3X1) defines the pin as an address; CADLOG3 = 0 (CATD = 0 for PSD3X1) defines it as a logic input. If it is an address, A19 can be latched with ALE (CADDHLT = 1) or be a transparent logic input (CADDHLT = 0). In this mode, there is no power-down capability. This user-programmable pin can be configured to reset on high level (CRESET = 1) or on low level (CRESET = 0). It should remain active for at least 100 ns. See Tables 10 and 11 and Figure 11 for reset details. In the multiplexed modes, the ALE pin functions as an Address Latch Enable or as an Address strobe and can be configured as an active high or active low signal. The ALE or AS trailing edge latches lines AD15/A15-AD0/A0 and A16-A19 in 16-bit mode (AD7/A7-AD0/A0 and A16-A19 in 8-bit mode) and BHE, depending on the PSD3XX configuration. See Table 8. In the non-multiplexed modes (PSD3X2/3X3), it can be used as a general-purpose logic input to the PAD. PA7-PA0 is an 8-bit port that can be configured to track AD7/A7-AD0/A0 from the input (CPAF2 = 1). Otherwise (CPAF2 = 0), each bit can be configured separately as an I/O or lower-order latched address line. When configured as an I/O (CPAF1 = 0), the direction of the pin is defined by its direction bit, which resides in the direction register. If a pin is an I/O output, its data bit (which resides in the data register) comes out. When it is configured as a low-order address line (CPAF1 =1), A7-A0 can be made the corresponding output through this port (e.g., PA6 can be configured to be the A6 address line). Each port bit can be a CMOS output (CPACOD = 0) or an open drain output (CPACOD = 1). When the chip is in non-multiplexed mode (CADDRAT = 0), the port becomes the data bus lines (D0-D7). See Figure 4. PB7-PB0 is an 8-bit port for which each bit can be configured as an I/O (CPBF = 1) or chip-select output (CPBF = 0). Each port bit can be a CMOS output (CPBCOD = 0) or an open drain output (CPBCOD = 1). When configured as an I/O, the direction of the pin is defined by its direction bit, which resides in the direction register. If a pin is an I/O output, its data (which resides in the data register) comes out. When configured as a chip-select output, CS0-CS3 are a function of up to four product terms of the inputs to the PAD B; CS4-CS7 then are each a function of up to two product terms. On the PSD301/302/303, when the chip is in non-multiplexed mode (CADDRAT = 0) and the data bus width is 16 (CDATA = 1), the port becomes the data bus (D8-D15). See Figure 6. A19/CSI I RESET I ALE or AS I PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 I/O PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 I/O 2-7 PSD3XX Family Table 1. PSD3XX Pin Descriptions (Cont.) Name Type Description This is a 3-bit port for which each bit is configurable as a PAD A and B input or output. When configured as an input (CPCF = 0),a bit individually becomes an address (CADLOG = 1 for PSD3X2/3X3, CATD = 1 for PSD3X1) or a logic input (CADLOG = 0 for PSD3X2/3X3, CATD = 0 for PSD3X1). The addresses can be latched with ALE (CADDHLT = 1) or be transparent inputs to the PADs (CADDHLT = 0). When a pin is configured as an output (CPCF = 1), it is a function of one product term of all PAD inputs. See Figure 7. In multiplexed mode, these pins are the multiplexed low-order address/data byte. After ALE latches the addresses, these pins input or output data, depending on the settings of the RD/E (RD/E/DS on the PSD302/312/303/313), WR/VPP or R/W, and BHE/PSEN pins. In non-multiplexed mode, these pins are the low-order address input. PC0 PC1 PC2 I/O AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 GND VCC I/O I/O In 16-bit multiplexed mode, these pins are the multiplexed high-order address/data byte. After ALE latches the addresses, these pins input or output data, depending on the settings of the RD/E or RD/E/DS, WR/VPP or R/W, and BHE/PSEN pins. In all other modes, these pins are the high-order address input. P P VSS (ground) pin. Supply voltage input. 2-8 PSD3XX Family Operating Modes The PSD3XX's four operating modes enable it to interface directly to 8- and 16-bit microcontrollers with multiplexed and non-multiplexed address/data buses. These operating modes are: t Multiplexed 8-bit address/data bus t Multiplexed 16-bit address/data bus (PSD30X) t Non-multiplexed address/data, 8-bit data bus t Non-multiplexed 16-bit address/data bus (PSD30X) Multiplexed 8-bit Address/Data Bus This mode is used to interface to microcontrollers with an 8-bit data bus and a 16-bit or larger address bus. The address/data bus (AD0/A0-AD7/A7) is bi-directional and permits the latching of the address when the ALE signal is active. On the same pins, the data is read from or written to the device; this depends on the state of the RD/E or RD/E/DS pin, BHE/PSEN or PSEN pin and WR/VPP or R/W pins. The high-order address/data bus (AD8/A8-AD15/A15) contains the high-order address bus byte. Ports A and B can be configured as in Table 2. Multiplexed 16-bit Address/Data Bus This mode is used to interface to microcontrollers with a 16-bit data bus and a 16-bit or larger address bus. The low-order address/data bus (AD0/A0-AD7/A7) is bi-directional and permits the latching of the address when the ALE signal is active. On the same pins, the data is read from or written to the device; this depends on the state of the RD/E/DS, BHE/PSEN, and WR/VPP or R/W pins. The high-order address/data bus (AD8/A8-AD15/A15) is bi-directional and permits latching of the high-order address when the ALE signal is active on the same pins. The high-order data bus is read from or written to the device, depending on the state of the RD/E/DS, BHE/PSEN, and WR/VPP or R/W pins. Ports A and B can be configured as in Table 2. Non-Multiplexed Address/Data, 8-bit Data Bus This mode is used to interface to non-multiplexed 8-bit microcontrollers with an 8-bit data bus and a 16-bit or larger address bus. The low-order address/data bus (AD0/A0-AD7/A7) is the low-order address input bus. The high-order address/data bus (AD8/A8-AD15/A15) (A8-A15 on the PSD31X) is the high-order address bus byte. Port A is the low-order data bus. Port B can be configured as shown in Table 2. Non-Multiplexed Address/Data, 16-bit Data Bus This mode is used to interface to non-multiplexed 16-bit microcontrollers with a 16-bit data bus and a 16-bit or larger address bus. The low-order address/data bus (AD0/A0-AD7/A7) is the low-order address input bus. The high-order address/data bus (AD8/A8-AD15/A15) is the high-order address bus byte. Port A is the low-order data bus. Port B is the high-order data bus. Table 2 summarizes the effect of the different operating modes on ports A, B, and the address/data pins. The configuration of Port C is independent of the four operating modes. 2-9 PSD3XX Family Figure 2a. PSD3XX Port Configurations (x8/x16) AD8- AD15 AD0-AD7 ALE BHE/ PSEN R / W or WR/ VPP RD/E/DS * A19/CSI RESET PC PB PA I /O or A0-A7 or AD0 -AD7 A8 -A15 AD0 -AD7 ALE PA I /O or A0-A7 or AD0 - AD7 I /O or CS0 - CS7 BHE /PSEN R/ W or WR/ VPP PB I /O or CS0 - CS7 A16 -A18 or CS8 - CS10 RD/E /DS * A19/CSI RESET PC A16 -A18 or CS8 - CS10 1. Configured for multiplexed 16-bit address/data bus. A8-A15 D0- D7 A0-A7 ALE BHE /PSEN R/ W or WR/ VPP RD/E/DS * A19/CSI RESET PC PB A16 -A18 or CS8 - CS10 D8 -D15 PA 2. Configured for multiplexed 8-bit address/data bus. A8 -A15 D0 - D7 A0 - A7 ALE BHE /PSEN R / W or WR/ VPP RD/E /DS * A19/CSI RESET PC PB A16 - A18 or CS8 - CS10 I /O or CS0 - CS7 PA 3. Configured for non-multiplexed 16-bit address/data bus. 4. Configured for non-multiplexed 8-bit address/data bus. Figure 2b. PSD31X Port Configurations (x8 Only) A8-A15 AD0- AD7 ALE PSEN R/W or WR/ VPP RD/E/DS* A19/CSI RESET PC PB PA I /O or A0-A7 or AD0 -AD7 A8 -A15 D0 -D7 A0 -A7 ALE PA I /O or CS0 - CS7 PSEN R / W or WR/ VPP PB I /O or CS0 - CS7 A16 - A18 or CS8 - CS10 RD/E /DS* A19/CSI RESET PC A16 - A18 or CS8 - CS10 1. Configured for multiplexed 8-bit address/data bus. 2. Configured for non-multiplexed 8-bit address/data bus. Legend: AD8-AD15 = Addresses A8-A15 multiplexed with data lines D8-D15. AD0-AD7 = Addresses A0-A7 multiplexed with data lines D0-D7. * = DS is available on PSD3X2/3X3/3X4R only. 2-10 PSD3XX Family Table 2. PSD30X Bus and Port Configuration Options Multiplexed Address/Data 8-bit Data Bus Port A Port B AD0/A0-AD7/A7 AD8/A8-AD15/A15 I/O or low-order address lines or low-order multiplexed address/data byte I/O and/or CS0-CS7 Low-order multiplexed address/data byte High-order multiplexed address data byte Non-Multiplexed Address/Data D0-D7 data bus byte I/O and/or CS0-CS7 Low-order address bus byte High-order address bus byte 16-bit Data Bus Port A Port B AD0/A0-AD7/A7 AD8/A8-AD15/A15 I/O or low-order address lines or low-order multiplexed address/data byte I/O and/or CS0-CS7 Low-order multiplexed address/data byte High-order multiplexed address/data byte Low-order data bus byte High-order data bus byte Low-order address bus byte High-order address bus byte Table 2a. PSD31X Bus and Port Configuration Options Multiplexed Address/Data 8-bit Data Bus Port A Port B AD0/A0-AD7/A7 A8-A15 I/O or low-order address lines or low-order multiplexed address/data byte I/O and/or CS0-CS7 Low-order multiplexed address/data byte High-order address bus byte Non-Multiplexed Address/Data D0-D7 data bus byte I/O and/or CS0-CS7 Low-order address bus byte High-order address bus byte Programmable Address Decoder (PAD) The PSD3XX consists of two programmable arrays referred to as PAD A and PAD B (Figure 3). PAD A is used to generate chip select signals derived from the input address to the internal EPROM blocks, SRAM, I/O ports, and Track Mode signals. All its I/O functions are listed in Table 3 and shown in Figure 3. PAD B outputs to Ports B and C for off-chip usage. PAD B can also be used to extend the decoding to select external devices or as a random logic replacement. The input bus to both PAD A and PAD B is the same. By using the PSDsoft Development Tools software, each programmable bit in the PAD array can have one of three logic states of 0, 1, and don't care (X). In a user's logic design, both PADs can share the same inputs, using the X for input signals that are not supposed to affect other functions. The PADs use reprogrammable CMOS EPROM technology and can be programmed and erased (if using windowed packages) by the user. 2-11 PSD3XX Family Figure 3. PAD Description P3 P2 ES0 ES1 ES2 ES3 ES4 ES5 ES6 ES7 RS0 8 EPROM BLOCK SELECT LINES P1 P0 ALE or AS PAD A SRAM BLOCK SELECT* I/O BASE ADDRESS TRACK MODE CONTROL SIGNALS RD/E/DS WR or R/W CSIOPORT CSADIN CSADOUT1 CSADOUT2 A19 CS0/PB0 A18 CS1/PB1 A17 A16 CS2/PB2 A15 CS3/PB3 CS4/PB4 A14 CS5/PB5 A13 CS6/PB6 A12 CS7/PB7 PAD B A11 CS8/PC0 CSI CS9/PC1 RESET CS10/PC2 *Not available on PSD3XXR versions. NOTES: 4. CSI is a power-down signal. When high, the PAD is in stand-by mode and all its outputs become non-active. See Tables 12 and 13. 5. RESET deselects all PAD output signals. See Tables 10 and 11. 6. A18, A17, and A16 are internally multiplexed with CS10, CS9, and CS8, respectively. Either A18 or CS10, A17 or CS9, and A16 or CS8 can be routed to the external pins of Port C. Port C can be configured as either input or output. 7. P0-P3 are not included on PSD3X1 devices. 8. DS is not available on PSD3X1 devices. 2-12 PSD3XX Family Table 3. PSD3XX PAD A and PAD B Functions Function PAD A and PAD B Inputs A19/CSI A16-A18 A11-A15 P0-P3 RD/E/DS WR or R/W ALE RESET In CSI mode (when high), PAD deselects all of its outputs and enters a power-down mode (see Tables 12 and 13). In A19 mode, it is another input to the PAD. These are general purpose inputs from Port C. See Figure 3, Note 6. These are address inputs. These are page number inputs (for the PSD302/312/303/313 only). This is the read pulse or enable strobe input. (Note 10) This is the write pulse or R/W select signal. This is the ALE input to the chip. This deselects all outputs from the PAD; it can not be used in product term equations. See Tables 10 and 11 and Figure 11. These are internal chip-selects to the 8 EPROM banks. Each bank can be located on any boundary that is a function of one product term of the PAD address inputs. This is an internal chip-select to the SRAM. Its base address location is a function of one term of the PAD address inputs. (Not available on PSD3XXR versions). This internal chip-select selects the I/O ports. It can be placed on any boundary that is a function of one product term of the PAD inputs. See Tables 6 and 7. This internal chip-select, when Port A is configured as a low-order address/data bus in the track mode (CPAF2 = 1), controls the input direction of Port A. CSADIN is gated externally to the PAD by the internal read signal. When CSADIN and a read operation are active, data presented on Port A flows out of AD0/A0-AD7/A7. This chip-select can be placed on any boundary that is a function of one product term of the PAD inputs. See Figure 5. This internal chip-select, when Port A is configured as a low-order address/data bus in track mode (CPAF2 = 1), controls the output direction of Port A. CSADOUT1 is gated externally to the PAD by the ALE signal. When CSADOUT1 and the ALE signal are active, the address presented on AD0/A0-AD7/A7 flows out of Port A. This chip-select can be placed on any boundary that is a function of one product term of the PAD inputs. See Figure 5. This internal chip-select, when Port A is configured as a low-order address/data bus in the track mode (CPAF2 = 1), controls the output direction of Port A. CSADOUT2 must include the write-cycle control signals as part of its product term. When CSADOUT2 is active, the data presented on AD0/A0-AD7/A7 flows out of Port A. This chip-select can be placed on any boundary that is a function of one product term of the PAD inputs. See Figure 5. These chip-select outputs can be routed through Port B. Each of them is a function of up to four product terms of the PAD inputs. These chip-select outputs can be routed through Port B. Each of them is a function of up to two product terms of the PAD inputs. These chip-select outputs can be routed through Port C. See Figure 3, Note 6. Each of them is a function of one product term of the PAD inputs. PAD A Outputs ES0-ES7 RS0 CSIOPORT CSADIN CSADOUT1 CSADOUT2 PAD B Outputs CS0-CS3 CS4 -CS7 CS8-CS10 2-13 PSD3XX Family Configuration Bits The configuration bits shown in Table 4 are non-volatile cells that let the user set the device, I/O, and control functions to the proper operational mode. Table 5 lists all configuration bits. The configuration bits are programmed and verified during the programming phase. In operational mode, they are not accessible. These tables are for information only since to implement to a specific mode, the PSDsoft Development software will automatically set the configuration bits by using simple interactive menus. Table 4. PSD3XX Non-Volatile Configuration Bits Use This Bit CDATA CADDRDAT CEDS CA19/CSI CALE CPAF2 CSECURITY CRESET COMB/SEP CPAF1 (8 Bits) CPACOD (8 Bits) CPBF (8 Bits) CPBCOD (8 Bits) CPCF (3 Bits) CADDHLT CADLOG (4 Bits) CATD CLOT CRRWR CRRWR CMISER To Set the data bus width to 8 or 16 bits (PSD30X only). Set the address/data buses to multiplexed or non-multiplexed mode. Determine the polarity and functionality of read and write. (Note 10) Set A19/CSI to CSI (power-down) or A19 input. Set the ALE polarity. Set Port A either to track the low-order byte of the address/data multiplexed bus or to select the I/O or address option. Set the security on or off (a secured part can not be duplicated). Set the RESET polarity. Set PSEN and RD for combined or separate address spaces (see Figures 9 and 10). Configure each pin of Port A in multiplexed mode to be an I/O or address out. Configure each pin of Port A as an open drain or active CMOS pull-up output. . Configure each pin of Port B as an I/O or a chip-select output Configure each pin of Port B as an open drain or active CMOS pull-up output. Configure each pin of Port C as an address input or a chip-select output. Configure pins A16 - A19 to go through a latch or to have their latch transparent. Configure A16 - A19 individually as logic or address inputs. (Note 10) Configure pins A16-A19 as PAD logic inputs or high-order address inputs (Note 9). Determine in non-multiplexed mode if address inputs are transparent or latched (Note 10). Set the RD/E and WR/VPP or R/W pins to RD and WR pulse, or to E strobe and R/W status (Note 9). Configure the polarity and control methods of read and write cycles. (Note 10) Controls the lower-power mode. NOTES: 9. PSD3X1 only. 10. PSD302/312/303/313/304R/314R only. This data sheet provides a complete listing of the function of each configuration bit in all control registers. In general, you will not need to be concerned about the details of most of these bits. The development software will set the bits automatically using information from your design files. 2-14 PSD3XX Family Table 5. PSD3XX Configuration Bits 11,12 Configuration Bits CDATA (Note 13) No. of Bits 1 Function 8-bit or 16-bit Data Bus Width CDATA = 0 eight bits CDATA = 1 sixteen bits ADDRESS/DATA Multiplexed (separate buses) CADDRDAT = 0, non-multiplexed CADDRDAT = 1, multiplexed A19 or CSI CA19/CSI = 0, enable power-down CA19/CSI = 1, enable A19 input to PAD Active HIGH or Active LOW CALE = 0, Active high CALE = 1, Active low Active high or active low CRESET = 0, active low reset signal CRESET = 1, active high reset signal Combined or Separate Address Space for SRAM and EPROM 0 = Combined, 1 = Separate Port A I/Os or A0-A7 CPAF1 = 0, Port A pin = I/O CPAF1 = 1, Port A pin = A0 - A7 Port A AD0-AD7 (address/data multiplexed bus) CPAF2 = 0, address or I/O on Port A (according to CPAF1) CPAF2 = 1, address/data multiplexed on Port A (track mode) A16-A19 address or logic inputs CATD = 0, logic inputs CATD = 1, address inputs A16-A19 Transparent or Latched CADDHLT = 0, Address latch transparent CADDHLT = 1, Address latched (ALE dependent) SECURITY On/Off CSECURITY = 0, off CSECURITY = 1, on A0-A15 Address Inputs are transparent or ALE-dependent in non-multiplexed modes CLOT = 0, transparent CLOT = 1, ALE-dependent Determine the polarity and control methods of read and write cycles. CEDS CRRWR 0 0 RD and WR active low pulses 0 1 R/W status and high E pulse 1 1 R/W status and low DS pulse CRRWR = 0, RD and WR active low strobes CRRWR = 1, R/W status and E active high pulse Port A CMOS or Open Drain Output CPACOD = 0, CMOS output CPACOD = 1, open-drain output CADDRDAT 1 CA19/CSI 1 CALE 1 CRESET 1 COMB/SEP 1 CPAF1 8 CPAF2 CATD (Note 15) CADDHLT 1 1 1 CSECURITY 1 CLOT (Note 14) 1 CRRWR CEDS (Note 14) 2 CRRWR (Note 15) CPACOD 1 8 2-15 PSD3XX Family Table 5. PSD3XX Configuration Bits (Cont.) Configuration Bits CPBF No. of Bits 8 Function Port B is I/O or CS0- CS7 CPBF = 0, Port B pin is CS0 - CS7 CPBF = 1, Port B pin is I/O Port B CMOS or Open Drain CPBCOD = 0, CMOS output CPBCOD = 1, open-drain output Port C A16-A18 or CS8-CS10 CPCF = 0, Port C pin is A16-A18 CPCF = 1, Port C pin is CS8-CS10 Port C: A16-A19 Address or Logic Input CADLOG = 0, Port C pin or A19/CSI is logic input CADLOG = 1, Port C pin or A19/CSI is address input Default: CMISER = 0 CMISER = 1, lower-power mode CPBCOD 8 CPCF CADLOG (Note 14) CMISER NOTES: 11. 12. 13. 14. 15. 3 4 1 The PSD Development software will guide the user to the proper configuration choice. In an unprogrammed or erased part, all configuration bits are 0. PSD30X only. PSD3X2/3X3 only. PSD3X1 only. Port Functions The PSD3XX has three I/O ports (Ports A, B, and C) that are configurable at the bit level. This permits great flexibility and a high degree of customization for specific applications. The following is a description of each port. Figure 4 shows the pin structure of Port A. Port A in Multiplexed Address/Data Mode The default configuration of Port A is I/O. In this mode, every pin can be set as an input or output by writing into the respective pin's direction flip flop (DIR FF, in Figure 4). As an output, the pin level can be controlled by writing into the respective pin's data flip flop (DFF, in Figure 4). When DIR FF = 1, the pin is configured as an output. When DIR FF = 0, the pin is configured as an input. The controller can read the DIR FF bits by accessing the READ DIR register; it can read the DFF bits by accessing the READ DATA register. Port A pin levels can be read by accessing the READ PIN register. Individual pins can be configured as CMOS or open drain outputs. Open drain pins require external pull-up resistors. For addressing information, refer to Tables 6 and 7. Alternatively, each bit of Port A can be configured as a low-order latched address bus bit. The address is provided by the port address latch, which latches the address on the trailing edge of ALE. PA0-PA7 can become A0-A7, respectively. This feature enables the user generate low-order address bits to access external peripherals or memory that require several low-order address lines. Another mode of Port A, i.e., Track Mode (CPAF2 = 1) sets the entire port to track the inputs AD0/A0-AD7/A7, depending on specific address ranges defined by the PAD's CSADIN, CSADOUT1, and CSADOUT2 signals. This feature lets the user interface the microcontroller to shared external resources without requiring external buffers and decoders. In this mode, the port is effectively a bi-directional buffer. The direction is controlled by using the input signals ALE, RD/E or RD/E/DS, WR/VPP or R/W, and the internal PAD outputs CSADOUT1, CSADOUT2 and CSADIN (see Figure 5). When CSADOUT1 and ALE are true, the address on the input AD0/A0-AD7/A7 pins is output through Port A. (Carefully check the generation of CSADOUT1, and ensure that it is stable during the ALE pulse. When CSADOUT2 is active, a write operation is performed (see note to Figure 5). The data on the input AD0/A0-AD7/A7 pins flows out through Port A. When CSADIN and a read operation is performed (depending on the mode of the RD/E or RD/E/DS, and WR/VPP or R/W pins), the data on Port A flows out through the AD0/A0-AD7/A7 pins. In this operational mode, Port A is tri-stated when none of the above-mentioned three conditions exist. 2-16 PSD3XX Family Figure 4. Port A Pin Structure I N T E R N A L A D D R / D A T A B U S A D 0 / A D 7 RESET READ PIN READ DATA CMOS /OD(16) WRITE DATA CK DFF D R ENABLE ALE ADDR G LATCH D R ADI / DI READ DIR MUX OUT PORT A PIN D WRITE DIR CK DIR FF R CONTROL NOTE: 16. CMOS/OD determines whether the output is open drain or CMOS. Figure 5. Port A Track Mode WR or R/W RD / E AD0-AD7 CONTROL DECODER INTERNAL READ I CSADIN PA0 - PA7 INTERNAL ALE O CSADOUT1 ALE or AS AD8- AD15 LATCH A11- A15 PAD CSADOUT2 (17) A16 - A19 NOTE: 17. The expression for CSADOUT2 must include the following write operation cycle signals: For CRRWR = 0, CSADOUT2 must include WR = 0. For CRRWR = 1, CSADOUT2 must include E = 1 and R/W = 0. 2-17 PSD3XX Family Port Functions (Cont.) Port A in Non-Multiplexed Address/Data Mode In this mode, Port A becomes the low order data bus byte of the chip. When reading an internal location, data is presented on Port A pins. When writing to an internal location, data present on Port A pins is written to that location. Port B in Multiplexed Address/Data and in 8-Bit Non-Multiplexed Modes The default configuration of Port B is I/O. In this mode, every pin can be set as an input or output by writing into the respective pin's direction flip flop (DIR FF, in Figure 6). As an output, the pin level can be controlled by writing into the respective pin's data flip flop (DFF, in Figure 6). When DIR FF = 1, the pin is configured as an output. When DIR FF = 0, the pin is configured as an input. The controller can read the DIR FF bits by accessing the READ DIR register; it can read the DFF bits by accessing the READ DATA register. Port B pin levels can be read by accessing the READ PIN register. Individual pins can be configured as CMOS or open drain outputs. Open drain pins require external pull-up resistors. For addressing information, refer to Tables 6 and 7. Alternately, each bit of Port B can be configured to provide a chip-select output signal from PAD B. PB0-PB7 can provide CS0-CS7, respectively. Each of the signals CS0-CS3 is comprised of four product terms.Thus, up to four ANDed expressions can be ORed while deriving any of these signals. Each of the signals CS4-CS7 is comprised of two product terms. Thus, up to two ANDed expressions can be ORed while deriving any of these signals. Port B in 16-Bit Non-Multiplexed Address/Data Mode (PSD30X) In this mode, Port B becomes the high-order data bus byte of the chip. When reading an internal high-order data bus byte location, the data is presented on Port B pins. When writing to an internal high-order data bus byte location, data present on Port B is written to that location. See Table 9. Accessing the I/O Port Registers Tables 6 and 7 show the offset values with the respect to the base address defined by the CSIOPORT. They let the user access the corresponding registers. Port C in All Modes Each pin of Port C (shown in Figure 7) can be configured as an input to PAD A and PAD B or output from PAD B. As inputs, the pins are named A16-A18. Although the pins are given names of the high-order address bus, they can be used for any other address lines or logic inputs to PAD A and PAD B. For example, A8-A10 can also be connected to those pins, improving the boundaries of CS0-CS7 resolution to 256 bytes. As inputs, they can be individually configured to be logic or address inputs. A logic input uses the PAD only for Boolean equations that are implemented in any or all of the CS0-CS10 PAD B outputs. Port C addresses can be programmed to latch the inputs by the trailing edge ALE or to be transparent. Alternately, PC0-PC2 can become CS8-CS10 outputs, respectively, providing the user with more external chip-select PAD outputs. Each of the signals CS8-CS10 is comprised of one product term. ALE/AS and A0 - A15 in Non-Multiplexed Modes (PSD3X2/3X3) In non-multiplexed modes, A0-A15 are address inputs only and can become transparent (CLOT = 0) or ALE dependent (CLOT = 1). In transparent mode, the ALE/AS pin can be used as an additional logic input to the PADs. The non-multiplexed ALE dependent mode is useful in applications for which the host processor has a multiplex address/data bus and AD0/A0-AD7/A7 are not multiplexed with A0-A7 but rather are multiplexed with other address lines. In these applications, Port A serves as a data bus and each of its pins can be directly connected to the corresponding host's multiplexed pin, where that data bit is expected. (See Table 8.) 2-18 PSD3XX Family Figure 6. Port B Pin Structure READ PIN I N T E R N A L C S O U T B U S I N T E R N A L D A T A B U S CSI D 8 READ DIR READ DATA CMOS/OD (18) WRITE DATA CK DFF D R DI MUX ENABLE OUT PORT B PIN C S 0 * * * 7 * * * D 1 5 RESET WRITE DIR D DIR CK FF R CONTROL NOTE: 18. CMOS/OD determines whether the output is open drain or CMOS. Table 6. I/O Port Addresses in an 8-bit Data Bus Mode Register Name Pin Register of Port A Direction Register of Port A Data Register of Port A Pin Register of Port B Direction Register of Port B Data Register of Port B Page Register Byte Size Access of the I/O Port Registers Offset from the CSIOPORT + 2 (accessible during read operation only) +4 +6 + 3 (accessible during read operation only) +5 +7 +18 Table 7. I/O Port Addresses in a 16-bit Data Bus Mode 19,20 (PSD30X) Register Name Pin Register of Ports B and A Direction Register of Ports B and A Data Register of Ports B and A Word Size Access of the I/O Port Registers Offset from the CSIOPORT + 2 (accessible during read operation only) +4 +6 NOTES: 19. When the data bus width is 16, Port B registers can only be accessed if the BHE signal is low. 20. I/O Ports A and B are still byte-addressable, as shown in Table 6. For I/O Port B register access, BHE must be low. 2-19 PSD3XX Family Figure 7. Port C Structure CADLOG0 CONF. BIT ADDRESS INDICATOR (NOTE 21) PC0 ADDRESS LATCH A16 TO PAD CS8 (OUTPUT LINE) CPCF0 CONF. BIT CADLOG1 CONF. BIT CADDHLT CONFIGURATION BIT: LATCH OR TRANSPARENT CONTROL FROM PAD ALE PC1 ADDRESS LATCH A17 TO PAD CS9 (OUTPUT LINE) CPCF1 CONF. BIT CADLOG2 CONF. BIT FROM PAD PC2 ADDRESS LATCH A18 TO PAD CS10 (OUTPUT LINE) CPCF2 CONF. BIT FROM PAD TO EPROM NOTES: 21. The CADDHLT configuration bit determines if A18-A16 are transparent via the latch, or if they must be latched by the trailing edge of the ALE strobe. 22. PSD3X2/3X3/3X4R: Individual pins can be configured independently as address or logic inputs (CADLOG, bits 0-2). PSD3X1: All Port C pins are either address or logic inputs (CATD). 2-20 PSD3XX Family A16 - A19 Inputs If one or more of the pins PC0, PC1 PC2 and CSI/A19 are configured as inputs, the configuration bits CADDHLT and CATD define their functionality inside the part. CADDHLT determines if these inputs are to be latched by the trailing edge of the ALE or AS signal (CADDHLT = 1), or enabled into the PSD3XX at all times (CADDHLT = 0, transparent mode). CATD determines whether these lines are high-order address lines, that take part in the derivation of EPROM select signals inside the chip (CATD = 1), or logic input lines that have no impact on memory or I/O selections (CATD = 0). Logic input lines typically participate in the Boolean expressions implemented in the PAD B. Unused input pins should be tied to VCC or GND. EPROM The EPROM has 8 banks of memory. Each bank can be placed in any address location by programming the PAD. Bank0-Bank7 is selected by PAD outputs ES0-ES7, respectively. Device EPROM Size EPROM Architecture x8 x16 16K x 16 - 32K x 16 - 64K x 16 - 128K x 16 - EPROM Bank Architecture (8 ea) x8 4K x 8 4K x 8 8K x 8 8K x 8 16K x 8 16K x 8 32K x 8 32K x 8 x16 2K x 16 - 4K x 16 - 8K x 16 - 16K x 8 - PSD301 PSD311 PSD302 PSD312 PSD303 PSD313 PSD304R PSD314R 256Kb 256Kb 512Kb 512Kb 1Mb 1Mb 2Mb 2Mb 32K x 8 32K x 8 64K x 8 64K x 8 128K x 8 128K x 8 256K x 8 256K x 8 SRAM Each PSD3XX device has 16K bits of SRAM (except the PSD3XXR versions which have no SRAM). Depending on the configuration of the data bus, the SRAM organization can be 2K x 8 (8-bit data bus) or 1K x 16 (16-bit data bus). The SRAM is selected by the RS0 output of the PAD. 2-21 PSD3XX Family Table 8. Signal Latch Status in All Operating Modes Signal Name Configuration Bits CDATA , CADDRDAT, CLOT = 0 CDATA, CADDRDAT = 0, CLOT = 1 Configuration Mode 8-bit data, non-multiplexed 16-bit data, non-multiplexed 8-bit data, multiplexed 16-bit data, multiplexed non-multiplexed modes multiplexed modes 8-bit data, PSEN is active 16-bit data, non-multiplexed mode, BHE is active 16-bit data, multiplexed mode, BHE is active A16-A19 can become logic inputs A16-A19 can become multiplexed address lines Signal Latch Status Transparent ALE Dependent Transparent ALE Dependent Transparent ALE Dependent Transparent ALE Dependent ALE Dependent Transparent CDATA = 1, CADDRDAT, CLOT = 0 AD8/A8- CDATA = 1, CADDRDAT = 0, CLOT = 1 AD15/A15 CDATA = 0, CADDRDAT = 1 CDATA = 1, CADDRDAT = 1 CADDRDAT = 0, CLOT = 0 AD0/A0AD7/A7 CADDRDAT = 0, CLOT = 1 CADDRDAT = 1 CDATA = 0 BHE/ PSEN CDATA = 1, CADDRDAT = 0 Transparent CDATA = 1, CADDRDAT = 1 A19 and PC2-PC0 ALE Dependent Transparent CADDHLT = 0 CADDHLT = 1 ALE Dependent 2-22 PSD3XX Family Memory Paging (PSD3X2/3X3/ 3X4R) The page register consists of four flip-flops, which can be read from, or written to, through the I/O address space (CSIOPORT). The page register is connected to the D3-D0 lines. The Page Register address is CSIOPORT + 18H. The page register outputs are P3-P0, which are fed into the PAD. This enables the host microcontroller to enlarge its address space by a factor of 16 (there can be a maximum of 16 pages). See Figure 8. Figure 8. Page Register (PSD3X2/3X3/ 3X4R) Q INTERNAL RESET CLR DFF CK D Q CLR DFF CK D Q CLR DFF CK D Q CLR DFF CK D P3 P2 P1 P0 TO PAD INPUTS INTERNAL WR PAGE SELECT INTERNAL RD AD3 AD2 AD1 AD0 DATA BUS 2-23 PSD3XX Family Control Signals The PSD3XX control signals are WR/VPP or R/W, RD/E or RD/E/DS, ALE or AS, BHE/PSEN or PSEN, RESET, and A19/CSI. Each of these signals can be configured to meet the output control signal requirements of various microcontrollers. WR/VPP or R/W In operational mode, this signal can be configured as WR or R/W. As WR, all write operations are activated by an active low signal on this pin. As R/W, the pin operates with the E strobe of the RD/E/DS or RD/E pin. When R/W is high, an active high signal on the RD/E/DS or RD/E pin performs a read operation. When R/W is low, an active high signal on the RD/E/DS or RD/E pin performs a write operation. RD/E/DS (or RD/E on PSD3X1) In operational mode, this signal can be configured as RD, E, or DS. As RD, all read operations are activated by an active low signal on this pin. As E, the pin operates with the R/W signal of the WR/VPP or R/W pin. When R/W is high, an active high signal on the RD/E/DS pin performs a read operation. When R/W is low, an active high signal on the RD/E/DS pin performs a write operation. As DS, the pin functions with the R/W signal as an active low data strobe signal. As DS, the R/W defines the mode of operation (Read or Write). ALE or AS ALE polarity is programmable. When programmed to be active high, a high on the pin causes the input address latches, Port A address latches, Port C, and A19 address latches to be transparent. The falling edge of ALE locks the information into the latches. When ALE is programmed to be active low, a low on the pin causes the input address latches, Port A address latches, Port C, and A19 address latches to be transparent. The rising edge of ALE locks the appropriate information into the latches. BHE/PSEN This pin's function depends on the PSD3XX data bus width. If it is 8 bits, the pin is PSEN; if it is 16 bits, the pin is BHE. In 8-bit mode, the PSEN function enables the user to work with two address spaces: program memory and data memory (if COMB/SEP = 1). In this mode, an active low signal on the PSEN pin causes the EPROM to be read if selected. The SRAM and I/O ports read operation are done by RD low (CRRWR = 0), or by E high and R/W high (CRRWR = 1, CEDS = 0) or by DS low and R/W high (CRRWR, CEDS = 1). Whenever a member of the 8031 family (or any other similar microcontroller) is used, the PSEN pin must be connected to the PSEN pin of the microcontroller. If COMB/SEP = 0, the address spaces of the program and the data are combined. In this configuration (except for the 8031-type case mentioned above), the PSEN pin must be tied high to VCC, and the EPROM, SRAM, and I/O ports are read by RD low (CRRWR = 0), or by E high and R/W high (CRRWR = 1, CEDS = 0) or by DS low and R/W high (CRRWR, CEDS = 1). See Figures 9 and 10. In BHE mode, this pin enables accessing of the upper-half byte of the data bus. A low on this pin enables a write or read operation to be performed on the upper half of the data bus (see Table 9). 2-24 PSD3XX Family Figure 9. Combined Address Space CS ADDRESS PAD SRAM* OE INTERNAL RD PSEN OE EPROM CS CS OE I/O PORTS *Not available on PSD3XXR versions. Figure 10. 8031-Type Separate Code and Data Address Spaces I/O PORTS OE INTERNAL RD CS OE CS ADDRESS PAD SRAM* CS EPROM PSEN OE *Not available on PSD3XXR versions. Table 9. High/Low Byte Selection Truth Table (in 16-Bit Configuration Only) BHE 0 0 1 1 A0 0 1 0 1 Operation Whole Word Upper Byte From/To Odd Address Lower Byte From/To Even Address None 2-25 PSD3XX Family Control Signals (Cont.) RESET This is an asynchronous input pin that clears and initializes the PSD3XX. Reset polarity is programmable (active low or active high). Whenever the PSD3XX reset input is driven active for at least 100 ns, the chip is reset. The PSD3XX must be reset at power up before it can be used. Tables 10 and 11 indicate the state of the part during and after reset. For the PSD3XXL, reset is an asynchronous low signal only. Whenever the reset input is driven low for at least 500 ns, the chip is reset. After reset becomes high, the chip will be operational only after an additional 500 ns. See Figure 11. Note that during boot-up, the part is not automatically reset internally and does require an external reset. Tables 10 and 11 indicate the state of the part during and after reset. A19/CSI When configured as CSI, a high on this pin deselects, and powers down, the chip. A low on this pin puts the chip in normal operational mode. For PSD3XX states during the power-down mode, see Tables 12 and 13, and Figure 12. In A19 mode, the pin is an additional input to the PAD. It can be used as an address line (CADLOG3 = 1) or as a general-purpose logic input (CADLOG3 = 0). A19 can be configured as ALE dependent or as transparent input (see Table 8). In this mode, the chip is always enabled. Table 10. Signal States During Reset Active (RESET) Signal AD0/A0-AD7/A7 A8-A15 PA0-PA7) (Port A) PB0-PB7 (Port B) PC0-PC2 (Port C) All Configuration Mode All I/O Tracking AD0/A0-AD7 Address outputs A0-A7 I/O CS7-CS0 CMOS outputs CS7-CS0 open drain outputs Address inputs A16-A18 CS8-CS10 CMOS outputs Condition Input Input Input Input Low Input High Tri-stated Input High Table 11. Internal States During and After Reset Cycle Component PAD Data register A Direction register A Data register B Direction register B Signals CS0-CS10 CSADIN, CSADOUT1, CSADOUT2, CSIOPORT, RS0, ES0 - ES7 n/a n/a n/a n/a Contents All = 1 (Note 23) All = 0 (Note 23) 0 0 0 0 NOTE: 23. All PAD outputs are in a non-active state. 2-26 PSD3XX Family Figure 11. The Reset Cycle (RESET) (PSD3XXL Only) VIH VIL 500 ns RESET LOW 500 ns RESET HIGH PSD3XX IS OPERATIONAL Table 12a. Signal States During Power-Down Mode (PSD30X) Signal AD0/A0-AD15/A15 PA0-PA7 Configuration Mode All I/O Tracking AD0/A0-AD7/A7 Address outputs A0-A7 I/O CS0-CS7 CMOS outputs CS0-CS7 open drain outputs Address inputs A18-A16 CS8-CS10 CMOS outputs Condition Input Unchanged Input All 1's Unchanged All 1's Tri-stated Input All 1's PB0-PB7 PC0-PC2 Table 12b. Signal States During Power-Down Mode (PSD31X) Signal AD0/A0-AD7/A7 A8-A15 PA0-PA7 All Configuration Mode All I/O Tracking AD0/A0-AD7/A7 Address outputs A0-A7 I/O CS0-CS7 CMOS outputs CS0-CS7 open drain outputs Address inputs A18-A16 CS8-CS10 CMOS outputs Condition Input Input Unchanged Input All 1's Unchanged All 1's Tri-stated Input All 1's PB0-PB7 PC0-PC2 2-27 PSD3XX Family Figure 12. A19/CSI Cell Structure CADLOG3 CONF. BIT (NOTE 24) ADDRESS INDICATOR TO EPROM CADDHLT CONFIGURATION BIT: LATCH OR TRANSPARENT CONTROL ALE A19 TO PAD TO PAD, EPROM, SRAM, PORTS, LATCHES, ETC. ADDRESS LATCH A19/CSI CSI (POWER-UP SIGNAL) CR19/CSI CONF. BIT NOTES: 24. The CADDHLT configuration bit determines if A19-A16 are transparent via the latch, or if they must be latched by the trailing edge of the ALE strobe. 25. In the PSD3X1, the CATD configuration bit performs this function for all the A16-A19 lines. Table 13. Internal States During Power-Down Component PAD Signals CS0-CS10 CSADIN, CSADOUT1, CSADOUT2, CSIOPORT, RS0, ES0-ES7 n/a n/a n/a n/a Contents All 1's (deselected) All 0's (deselected) Data register A Direction register A Data register B Direction register B All unchanged 2-28 PSD3XX Family Figure 13. PSD3XX Interface With Intel's 80C31 31 19 VCC MICROCONTROLLER EA/VP X1 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 23 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 22 2 1 13 3 AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 0.1F 44 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 A19/CSI GND 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 40 41 42 43 18 X2 9 RESET 12 13 14 15 1 2 3 4 5 6 7 8 INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 RD WR/VPP BHE/PSEN ALE RESET 80C31 PSD3XX 34 12 NOTE: RESET to the PSD3XX must be the output of a RESET chip or buffer. If RESET to the 80C31 is the output of an RC circuit, a separate buffered RC RESET to the PSD3XX (shorter than the 80C31 RC RESET) must be provided to avoid a race condition. The configuration bits for Figure 13 are: CALE 0 CDATA 0 CADDRDAT 1 CRESET 1 COMB/SEP CRRWR CEDS 0 or 1 (both valid) 0 0 All other configuration bits may vary according to the application requirements. System Applications In Figure 13, the PSD3XX is configured to interface with Intel's 80C31, which is a 16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order address byte. The 80C31 uses signals RD to read from data memory and PSEN to read from code memory. It uses WR to write into the data memory. It also uses active high reset and ALE signals. The rest of the configuration bits as well as the unconnected signals (not shown) are application specific and, thus, user dependent. In Figure 14, the PSD3XX is configured to interface with Motorola's 68HC11, which is a 16-bit address/8-bit data bus microcontroller. Its data bus is multiplexed with the low-order address byte. The 68HC11 uses E and R/W signals to derive the read and write strobes. It uses the term AS (address strobe) for the address latch pulse. RESET is an active low signal. The rest of the configuration bits as well as the unconnected signals (not shown) are specific and, thus, user dependent. 2-29 PSD3XX Family Figure 14. PSD3XX Interface With Motorola's 68HC11 20 21 22 23 24 25 43 45 47 49 44 46 48 50 34 33 32 31 30 29 28 27 52 51 VCC MICROCONTROLLER PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 E R/W AS RESET XIRQ IRQ MODB MODA XTAL EXTAL 9 10 11 12 13 14 15 16 42 41 40 39 38 37 36 35 5 6 4 17 18 19 2 3 23 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 22 2 13 3 1 0.1F 44 AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 E R/W/VPP AS RESET BHE/PSEN PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 A19/CSI 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 40 41 42 43 PD0 PD1 PD2 PD3 PD4 PD5 PE0 PE1 PE2 PE3 PD4 PE5 PE6 PE7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VRH VRL VCC GND PSD3XX 34 12 68HC11 The configuration bits for Figure 14 are: CALE 0 CDATA 0 CADDRDAT 1 CRESET 0 COMB/SEP CRRWR CEDS 0 1 0 All other configuration bits may vary according to the application requirements. System Applications (Cont.) In Figure 15, the PSD3XX is configured to work directly with Intel's 80C196KB microcontroller, which is a 16-bit address/16-bit data bus processor. Address and data lines multiplexed. In the example shown, all configuration bits are set. The PSD3XX is configured to use PC0, PC1, PC2, and CSI/A19 as A16, A17, A18, and A19 inputs, respectively. These signals are independent of the ALE pulse (latch-transparent). They are used as four general-purpose logic inputs that take part in the PAD equations implementation. Port A is configured to work in the special track mode, in which (for certain conditions) PA0-PA7 tracks lines AD0/A0-AD7/A7. Port B is configured to generate CS0-CS7. In this example, PB2 serves as a WAIT signal that slows down the 80C196KB during the access of external peripherals. These 8-bit wide peripherals are connected to the shared bus of Port A. The WAIT signal also drives the buswidth input of the microcontroller, so that every external peripheral cycle becomes an 8-bit data bus cycle. PB3 and PB4 are open-drain output signals; thus, they are pulled up externally. 2-30 PSD3XX Family Figure 15. PSD3XX Interface With Intel's 80C196KB. +5V +5V 0.1F ADDRESS/DATA MULTIPLEXED BUS P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0/AD0 P3.1/AD1 P3.2/AD2 P3.3/AD3 P3.4/AD4 P3.5/AD5 P3.6/AD6 P3.7/AD7 P4.0/AD8 P4.1/AD9 P4.2/AD10 P4.3/AD11 P4.4/AD12 P4.5/AD13 P4.6/AD14 P4.7/AD15 CLKOUT BHE/ WRH WR/ WRL RD ALE /ADV INST HSO.0 HSO.1 HSO.2 HSO.3 VSS VSS 36 19 20 21 22 23 30 31 32 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 65 41 40 61 62 63 28 29 34 35 AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 44 VCC AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 23 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 40 41 42 43 1 2 22 13 3 AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 PC0 PC1 PC2 A19/CSI BHE /PSEN WR/ VPP RD ALE RESET GND GND PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 0.1F VCC 67 XTAL1 AD[0 ..15] AD[0 ..15] 66 NMI 3 43 64 14 16 6 5 7 4 11 10 8 9 RxD TxD 18 17 15 44 42 39 33 38 24 25 26 27 +5V 13 37 12 2 XTAL2 NMI READY BUSWIDTH CDE RESET P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0/TXD P2.1/RXD P2.2/EXINT P2.3/T2CLK P2.4/T2RST P2.5/PWM P2.6/ T2 UP/DN P2.7/ T2 CAPTR HSI.0 HSI.1 HSI.2/HSO.4 HSI.3/HSO.5 VREF VPP ANGND EA PORT 1 I/O PINS RST 21 20 19 18 17 16 15 14 11 10 9 8 7 6 5 4 SHARED BUS WAIT 4.7K 4.7K 0.1F +5V 80C196KB 68 PSD3XX 12 34 ALE FOUR GENERAL PURPOSE INPUTS The configuration bits for Figure 15 are: CALE 0 CDATA 1 CADDRDAT 1 CPAF1 Don't care CPAF2 1 CA19/CSI 1 CRRWR 0 COMB/SEP 0 CADDHLT 0 CRESET 0 CSECURITY CPCF2, CPCF1, CPCF0 CPACOD7-CPACOD0 CPBF7-CPBF0 CPBCOD7-CPBCOD0 CEDS CADLOG3--CADLOG0 Don't care 0, 0, 0 00H 00H 18H 0 0H 2-31 PSD3XX Family Security Mode Security Mode in the PSD3XX locks the contents of the PAD A , PAD B and all the configuration bits. The EPROM, SRAM, and I/O contents can be accessed only through the PAD. The Security Mode can be set by the PSD Development or Programming software. In window packages, the mode is erasable through UV full part erasure. In the security mode, the PSD3XX contents cannot be copied on a programmer. The EPROM power consumption in the PSD is controlled by bit 3 in the PMMR0 - EPROM CMiser. Upon reset the CMiser bit is OFF. This will cause the EPROM to be ON at all times as long as CSI is enabled (low). The reason this mode is provided is to reduce the access time of the EPROM by 10 ns relative to the low power condition when CMiser is ON. If CSI is disabled (high) the EPROM will be deselected and will enter standby mode (OFF) overriding the state of the CMiser. If CMiser is set (ON) then the EPROM will enter the standby mode when not selected. This condition can take place when CSI is high or when CSI is low and the EPROM is not accessed. For example, if the MCU is accessing the SRAM, the EPROM will be deselected and will be in low power mode. An additional advantage of the CMiser is achieved when the PSD is configured in the by 8 mode (8 bit data bus). In this case an additional power savings is achieved in the EPROM (and also in the SRAM) by turning off 1/2 of the array even when the EPROM is accessed (the array is divided internally into odd and even arrays). The power consumption for the different EPROM modes is given in the DC Characteristics table under ICC (DC) EPROM Adder. EPROM Absolute Maximum Ratings 26 Symbol TSTG Parameter Storage Temperature Voltage on any Pin Condition CERDIP PLASTIC With Respect to GND With Respect to GND With Respect to GND Min - 65 - 65 - 0.6 - 0.6 - 0.6 Max + 150 + 125 +7 + 14 +7 Unit C C V V V V VPP VCC Programming Supply Voltage Supply Voltage ESD Protection >2000 NOTE: 26. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Operating Range Range Commercial Industrial Military Temperature 0 C to +70C -40 C to +85C -55 C to +125C VCC +5V +5V +5V VCC Tolerance 10% 10% 10% Recommended Operating Conditions Symbol VCC VCC Parameter Supply Voltage Supply Voltage Conditions All Speeds PSD3XXL Versions Only, All Speeds Min 4.5 3.0 Typ Max Unit 5 3.3 5.5 5.5 V V 2-32 PSD3XX Family DC Characteristics - PSD3XX Versions (5V 10%) CMiser = 1 Subtract: Symbol VIH VIL Parameter High-Level Input Voltage Low-Level Input Voltage Conditions VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V IOH = - 20 A, VCC = 4.5 V IOH = - 2 mA, VCC = 4.5 V IOL = 20 A VCC = 4.5 V IOL = 8 mA VCC = 4.5 V Comm'l Ind/Mil Comm'l (Note 31) Comm'l (Note 32) Ind/Mil (Note 31) Ind/Mil (Note 32) Comm'l (Note 31) Min 2 - 0.5 4.4 2.4 Typ Max VCC + .1 0.8 Min Typ Max Unit V V V V 4.49 3.9 0.01 0.15 50 75 16 28 16 28 16 28 16 28 47 59 47 59 0.1 0.45 100 150 35 50 45 60 35 50 45 60 80 95 100 115 1 10 7 7 7 7 0/5* 0/5* 0/5* 0/5* 7 7 7 7 10 10 10 10 0/7* 0/7* 0/7* 0/7* 10 10 10 10 VOH Output High Voltage V V A A mA mA mA mA mA mA mA mA mA mA mA mA A A VOL Output Low Voltage ISB1 VCC Standby Current (CMOS) (Notes 27 and 29) Active Current (CMOS) (No Internal Memory Block Selected) (Notes 27, 28a and 30) ICC1 ICC2 Active Current (CMOS) (EPROM Block Selected) (Notes 27, 28a and 30) Comm'l (Note 32) Ind/Mil (Note 31) Ind/Mil (Note 32) Comm'l (Note 31) ICC3 Active Current (CMOS) (SRAM Block Selected) (Notes 27, 28a and 30) Input Leakage Current Output Leakage Current Comm'l (Note 32) Ind/Mil (Note 31) Ind/Mil (Note 32) ILI ILO VIN = 5.5 V or GND VOUT = 5.5 V or GND -1 -10 0.1 5 NOTES: 27. CMOS inputs: GND 0.3 V or VCC 0.3V. 28. TTL inputs: VIL 0.8 V, VIH 2.0 V. 28a. I OUT = 0 mA. 29. CSI/A19 is high and the part is in a power-down configuration mode. 30. Add 3.0 mA/MHz for AC power component (power = AC + DC). 31. Ten (10) PAD product terms active. (Add 380 A per product term, typical, or 480 A per product term maximum.) 32. Forty-one (41) PAD product terms active. *The zero value is for 16-bit configurations. The other values are for 8-bit configurations. 2-33 PSD3XX Family DC Characteristics - PSD3XXL Low-Power Versions (3.3V 10%) CMiser = 1 Subtract: Symbol VIH VIL Parameter High-Level Input Voltage Low-Level Input Voltage Conditions Min Typ Max VCC + 0.5 0.3 VCC Min Typ Max Unit V V V V VCC = 3.0 V to 5.5 V 0.7 VCC VCC = 3.0 V to 5.5 V IOH = - 20 A, VCC = 3.0 V IOH = - 1 mA, VCC = 3.0 V IOL = 20 A, VCC = 3.0 V IOL = 4 mA, VCC = 3.0 V - 0.5 2.9 2.4 2.99 2.6 0.01 0.15 1 5 9 5 9 16 21 -1 -10 0.1 5 VOH Output High Voltage 0.1 0.4 5 11 17 11 17 29 35 1 10 3.0 3.0 0/2* 0/2* 3 3 4 4 0/3* 0/3* 4 4 V V A mA mA mA mA mA mA A A VOL Output Low Voltage ISB1 VCC Standby Current VCC = 3.3 V (CMOS) (Notes 33 and 34) Active Current (CMOS) (No Internal Memory Block Selected) (Notes 33, 33a and 35) Active Current (CMOS) (EPROM Block Selected) (Notes 33, 33a and 35) VCC = 3.3 V (Note 36) VCC = 3.3 V (Note 37) VCC = 3.3 V (Notes 36 and 38) VCC = 3.3 V (Notes 37 and 38) VCC = 3.3 V (Notes 36 and 38) VCC = 3.3 V (Notes 37 and 38) VIN = VCC or GND VOUT = VCC or GND ICC1 ICC2 ICC3 Active Current (CMOS) (SRAM Block Selected) (Notes 33, 33a and 35) Input Leakage Current Output Leakage Current ILI ILO NOTES: 33. 33a. 34. 35. CMOS inputs: GND 0.3 V or VCC 0.3V. I OUT = 0 mA. CSI/A19 is high and the part is in a power-down configuration mode. AC power component (power = AC + DC). - For 3.3 V operation, add 2.0 mA/MHz. - For 5.0 V operation, add 3.0 mA/MHz. 36. Ten (10) PAD product terms active. (Add 190 A per product term, typical, or 240 A per product term maximum.) 37. Forty (40) PAD product terms active. 38. In 8-bit mode, an additional 3 mA Max can be saved under CMiser. *The zero value is for 16-bit configurations. The other values are for 8-bit configurations. 2-34 PSD3XX Family NORMALIZED SUPPLY CURRENT MULTIPLIER Figure 16. Normalized Supply Current vs. Supply Voltage (PSD3XXL Low-Power Versions) 3.5 3.0 2.5 DC 2.0 1.5 1.0 0.5 3.0 3.3 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) The Normalized Supply Current vs. Supply Voltage graph shown above, provides a multiplier for any ISB or ICC value in the D.C. Characteristics table. As noted, it is normalized for a supply voltage of 3.3 volts (PSD3XXL versions). To use, calculate the supply current at 3.3 volts for your operation configuration using the D.C. Characteristics table. Then multiply that value by the Supply Current Multiplier for the supply voltage actually being used. NORMALIZED ACCESS TIME MULTIPLIER (T6) Figure 16a. Normalized Access Time Multiplier vs. Supply Voltage (PSD3XXL Low-Power Versions) 1.0 0.9 0.8 0.7 0.6 0.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 2-35 PSD3XX Family AC Characteristics - PSD3XX Versions (5V 10%) Symbol T1 T2 T3 T4 T5 T6 T7 T8 Parameter ALE or AS Pulse Width Address Set-up Time Address Hold Time Leading Edge of Read to Data Active ALE Valid to Data Valid Address Valid to Data Valid CSI Active to Data Valid Leading Edge of Read to Data Valid Leading Edge of Read to Data Valid in 8031-Based Architecture Operating with PSEN and RD in Separate Mode Read Data Hold Time Trailing Edge of Read to Data High-Z (PSD3X1) CMiser On = Unit Min Max Min Max Min Max Min Max Min Max Add 18 5 7 0 80 70 80 20 20 5 8 0 100 90 100 32 30 9 9 0 140 120 150 36 40 12 10 0 170 150 160 45 50 15 15 0 200 210 200 50 0 0 0 0 10 10 10 0 ns ns ns ns ns ns ns ns -70 -90 -12 -15 -20 T8A 32 32 38 55 60 0 ns T9 0 20 0 35 0 35 0 40 0 45 0 0 ns ns T10 Trailing Edge of Read to Data High-Z (PSD3X2/3X3/3X4R) Trailing Edge of ALE or AS to Leading Edge of Write RD, E, PSEN, or DS Pulse Width WR Pulse Width Trailing Edge of Write or Read to Leading Edge of ALE or AS Address Valid to Trailing Edge of Write CSI Active to Trailing Edge of Write Write Data Set-up Time 0 20 30 35 40 45 0 ns T11 0 0 0 0 0 ns T12 T12A T13 35 18 5 40 20 5 45 25 5 60 35 5 75 45 5 0 0 0 ns ns ns T14 T15 T16 70 80 18 90 100 20 120 130 25 150 160 30 200 200 40 0 0 0 ns ns ns 2-36 PSD3XX Family AC Characteristics - PSD3XX Versions (5V 10%) (Cont.) Symbol T17 T18 T19 T20 T21 T22 Parameter Write Data Hold Time Port to Data Out Valid Propagation Delay Port Input Hold Time Trailing Edge of Write to Port Output Valid ADi or Control to CSOi Valid ADi or Control to CSOi Invalid Track Mode Address Propagation Delay: CSADOUT1 Already True Latched Address Outputs, Port A Track Mode Address Propagation Delay: CSADOUT1 Becomes True During ALE or AS Track Mode Trailing Edge of ALE or AS to Address High-Z Track Mode Read Propagation Delay Track Mode Read Hold Time Track Mode Write Cycle, Data Propagation Delay Track Mode Write Cycle, Write to Data Propagation Delay Hold Time of Port A Valid During Write CSOi Trailing Edge CSI Active to CSOi Active (PSD3X1) CMiser On = Unit Min Max Min Max Min Max Min Max Min Max Add 5 25 0 30 6 5 20 20 6 5 0 35 25 25 6 5 5 28 0 40 30 30 6 4 5 30 0 50 35 35 5 4 10 35 0 60 45 45 15 45 0 0 0 0 10 10 ns ns ns ns ns ns -70 -90 -12 -15 -20 22 22 22 22 28 0 ns T23 22 22 22 22 28 0 ns T23A 33 33 33 40 50 10 ns T24 30 32 32 35 40 0 ns T25 T26 T27 27 5 29 18 11 29 29 20 11 29 29 20 11 29 29 20 11 35 35 30 0 0 0 ns ns ns T28 6 30 8 30 8 30 9 40 9 55 0 ns T29 2 2 2 2 2 0 ns 8 8 8 0 37 37 37 9 9 9 0 40 40 40 9 9 9 0 45 45 45 9 9 9 0 45 50 45 8 8 8 0 60 60 60 0 0 0 0 ns ns ns ns T30 CSI Active to CSOi Active (PSD3X2/3X3/3X4R) CSI Inactive to CSOi Inactive Direct PAD Input as Hold Time T31 T32 2-37 PSD3XX Family AC Characteristics - PSD3XX Versions (5V 10%) (Cont.) Symbol Parameter R/W Active to E High (PSD3X1) T33 R/W Active to E or DS Start (PSD3X2/3X3/3X4R) E End to R/W (PSD3X1) T34 E or DS End to R/W (PSD3X2/3X3/3X4R) AS Inactive to E high Address to Leading Edge of Write CMiser On = Unit Min Max Min Max Min Max Min Max Min Max Add 18 18 18 18 0 18 20 20 20 20 0 20 20 20 20 20 0 20 30 30 30 30 0 25 40 40 40 40 0 30 0 0 0 0 0 0 ns ns ns ns ns ns -70 -90 -12 -15 -20 T35 T36 NOTES: 39. ADi = any address line. 40. CSOi = any of the chip-select output signals coming through Port B (CS0-CS7) or through Port C (CS8-CS10). 41. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E/DS, WR or R/W, transparent PC0-PC2, ALE (or AS). 42. Control signals RD/E/DS or WR or R/W. Figure 17. PSD3XX IOL vs. VOL 40 35 30 25 IOL (mA) 20 15 10 Temp. = 125C Temp. = 25C 5 0 0.00 0.10 0.20 0.30 0.40 VOL (V) 0.50 0.60 0.70 0.80 2-38 PSD3XX Family AC Characteristics - PSD3XXL Low-Power Versions (3.3V 10%, Note 43) CMiser =1 Min Max Min Max Min Max Min Max Add: Unit 40 12 10 0 160 150 160 40 60 0 40 0 60 35 5 0 75 45 5 100 90 5 250 275 60 25 45 0 50 6 4 45 45 5 4 60 50 50 6 4 0 100 80 80 5 4 70 0 110 85 85 0 45 50 15 15 0 200 200 210 45 65 0 55 40 110 95 5 300 325 65 30 75 75 30 20 0 250 250 275 90 90 0 60 45 0 0 0 0 0 0 0 0 0 0 0 0 80 35 30 0 300 300 325 95 95 0 0 20 20 20 0 0 0 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns -15 -20 -25 -30 Symbol T1 T2 T3 T4 T5 T6 T7 T8 T8A T9 T10 T11 T12 T12A T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Parameter ALE or AS Pulse Width Address Set-up Time Address Hold Time Leading Edge of Read to Data Active ALE Valid to Data Valid Address Valid to Data Valid CSI Active to Data Valid Leading Edge of Read to Data Valid Leading Edge of Read to Data Valid Read Data Hold Time Trailing Edge of Read to Data High-Z Trailing Edge of ALE or AS to Leading Edge of Write RD, E, PSEN, DS Pulse Width WR Pulse Width Trailing Edge of Write or Read to Leading Edge of ALE or AS Address Valid to Trailing Edge of Write CSI Active to Trailing Edge of Write Write Data Set-up Time Write Data Hold Time Port to Data Out Valid Propagation Delay Port Input Hold Time Trailing Edge of Write to Port Output Valid ADi or Control to CSOi Valid ADi or Control to CSOi Invalid 150 160 30 10 40 0 200 200 40 12 NOTE: 43. These AC Characteristics are for VCC = 3.0 - 3.6V. 2-39 PSD3XX Family AC Characteristics - PSD3XXL Low-Power Versions (3.3V 10%, Note 43 ) -15 -20 -25 -30 (Cont.) Symbol T23 Parameter Track Mode Address Propagation Delay: CSADOUT1 Already True Latched Address Outputs, Port A Track Mode Address Propagation Delay: CSADOUT1 Becomes True During ALE or AS Track Mode Trailing Edge of ALE or AS to Address High-Z Track Mode Read Propagation Delay Track Mode Read Hold Time Track Mode Write Cycle, Data Propagation Delay Track Mode Write Cycle, Write to Data Propagation Delay Hold Time of Port A Valid During Write CSOi Trailing Edge CSI Active to CSOi Active CSI Inactive to CSOi Inactive Direct PAD Input as Hold Time R/W Active to E or DS Start E or DS End to R/W AS Inactive to E high Address to Leading Edge of Write CMiser =1 Min Max Min Max Min Max Min Max Add: Unit 50 60 70 75 0 ns 50 60 70 75 0 T23A 70 80 100 110 0 ns T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 45 40 10 70 40 8 2 9 9 0 30 30 0 25 55 55 65 8 3 9 9 0 40 40 0 30 10 55 50 70 50 75 9 4 70 70 9 9 0 60 60 40 50 10 60 70 70 60 80 9 4 110 110 8 8 0 65 65 45 60 10 65 75 75 65 85 0 0 ns ns ns 0 0 0 ns ns ns ns ns ns ns ns ns ns 120 120 0 0 0 0 0 0 0 NOTES: 44. ADi = any address line. 45. CSOi = any of the chip-select output signals coming through Port B (CS0-CS7) or through Port C (CS8-CS10). 46. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E/DS, WR or R/W, transparent PC0-PC2, ALE (or AS). 47. Control signals RD/E/DS or WR or R/W. 2-40 PSD3XX Family Figure 18. Timing of 8-Bit Multiplexed Address/Data Bus, CRRWR = 0 (PSD3X1) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input 15 32 STABLE INPUT 6 Multiplexed (49) Inputs 6 A0/AD0A7/AD7 Active High ALE Active Low ALE ADDRESS A 2 1 3 10 DATA VALID 9 2 14 ADDRESS B 3 16 1 11 4 8 12 RD/E as RD 5 BHE/PSEN as PSEN WR/VPP or RW as WR Any of PA0-PA7 as I/O Pin Any of PB0-PB7 as I/O Pin Any of PA0-PA7 Pins as Address Outputs 23 ADDRESS A 36 13 17 DATA IN STABLE INPUT 14 WRITE CYCLE 32 12A 13 18 INPUT 19 20 OUTPUT INPUT 23 ADDRESS B OUTPUT See referenced notes on page 2-61. 2-41 PSD3XX Family Figure 19. Timing of 8-Bit Multiplexed Address/Data Bus, CRRWR = 0 (PSD3X2/3X3/3X4R) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input 15 32 STABLE INPUT 6 Multiplexed (49) Inputs 6 A0/AD0A7/AD7 Active High ALE Active Low ALE ADDRESS A 2 1 3 DATA VALID 9 2 10 14 ADDRESS B 3 16 1 4 8 12 RD/E/DS as RD 5 BHE/PSEN as PSEN WR/VPP or RW as WR Any of PA0-PA7 as I/O Pin Any of PB0-PB7 as I/O Pin Any of PA0-PA7 Pins as Address Outputs 23 ADDRESS A 11 17 DATA IN STABLE INPUT 14 WRITE CYCLE 32 13 36 12A 13 18 INPUT 19 20 OUTPUT INPUT 23 ADDRESS B OUTPUT See referenced notes on page 2-61. 2-42 PSD3XX Family Figure 20. Timing of 8-Bit Multiplexed Address/Data Bus, CRRWR = 1 (PSD3X1) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input 15 32 STABLE INPUT 6 Multiplexed (49) Inputs 6 A0/AD0A7/AD7 Active High AS Active Low AS ADDRESS A 2 1 3 10 DATA VALID 9 2 14 ADDRESS B 3 16 1 17 DATA IN STABLE INPUT 14 WRITE CYCLE 32 35 4 13 35 33 34 12 36 33 12 13 RD/E as E 5 8 34 WR/VPP or R/W as R/W 18 Any of PA0-PA7 as I/O Pin Any of PB0-PB7 as I/O Pin Any of PA0-PA7 Pins as Address Outputs 23 ADDRESS A INPUT 19 20 OUTPUT INPUT 23 ADDRESS B OUTPUT See referenced notes on page 2-61. 2-43 PSD3XX Family Figure 21. Timing of 8-Bit Multiplexed Address/Data Bus, CRRWR = 1 (PSD3X2/3X3/3X4R) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input 15 32 STABLE INPUT 6 Multiplexed (49) Inputs 6 A0/AD0A7/AD7 Active High AS Active Low AS ADDRESS A 2 1 3 10 DATA VALID 9 2 14 ADDRESS B 3 16 1 17 DATA IN STABLE INPUT 14 WRITE CYCLE 32 35 4 13 35 33 34 RD/E/DS as E 5 RD/E/DS as DS 33 WR/VPP or R/W as R/W 18 Any of PA0-PA7 as I/O Pin Any of PB0-PB7 as I/O Pin Any of PA0-PA7 Pins as Address Outputs 23 8 34 36 12 12 13 19 INPUT 20 OUTPUT INPUT 23 ADDRESS A ADDRESS B OUTPUT See referenced notes on page 2-61. 2-44 PSD3XX Family Figure 22. Timing of 16-Bit Multiplexed Address/Data Bus, CRRWR = 0 (PSD3X1) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input 15 32 STABLE INPUT 6 Multiplexed (49) Inputs 6 10 14 STABLE INPUT 14 WRITE CYCLE 32 BHE/PSEN as BHE A0/AD0A15/AD15 Active High ALE Active Low ALE 5 12 RD/E as RD DATA IN ADDRESS A 2 1 3 4 1 8 13 DATA VALID 9 2 ADDRESS B 3 16 17 11 36 13 12A WR/VPP or R/W as WR 18 Any of PA0-PA7 as I/O Pin Any of PB0-PB7 as I/O Pin Any of PA0-PA7 Pins as Address Outputs INPUT 19 20 OUTPUT INPUT 23 ADDRESS A 23 ADDRESS B OUTPUT See referenced notes on page 2-61. 2-45 PSD3XX Family Figure 23. Timing of 16-Bit Multiplexed Address/Data Bus, CRRWR = 0 (PSD3X2/3X3/3X4R) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input 15 32 STABLE INPUT 6 Multiplexed (49) Inputs 6 14 STABLE INPUT 14 WRITE CYCLE 32 BHE/PSEN as BHE A0/AD0A15/AD15 Active High ALE Active Low ALE 5 12 RD/E/DS as RD 10 DATA IN ADDRESS B 2 3 16 1 17 ADDRESS A 2 1 3 4 DATA VALID 9 8 13 11 36 13 12A WR/VPP or R/W as WR 18 Any of PA0-PA7 as I/O Pin Any of PB0-PB7 as I/O Pin Any of PA0-PA7 Pins as Address Outputs INPUT 19 20 OUTPUT INPUT 23 ADDRESS A 23 ADDRESS B OUTPUT See referenced notes on page 2-61. 2-46 PSD3XX Family Figure 24. Timing of 16-Bit Multiplexed Address/Data Bus, CRRWR = 1 (PSD3X1) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input 15 32 STABLE INPUT 6 Multiplexed (49) Inputs 6 10 14 STABLE INPUT 14 WRITE CYCLE 32 BHE/PSEN as BHE A0/AD0A15/AD15 Active High AS Active Low AS RD/E as E 5 WR/VPP or R/W as R/W Any of PA0-PA7 as I/O Pin Any of PB0-PB7 as I/O Pin 23 Any of PA0-PA7 Pins as Address Outputs ADDRESS A DATA IN ADDRESS A 2 1 3 DATA VALID 9 2 ADDRESS B 3 16 1 35 17 4 13 34 12 35 33 12 34 13 33 8 18 INPUT 19 36 20 OUTPUT INPUT 23 ADDRESS B OUTPUT See referenced notes on page 2-61. 2-47 PSD3XX Family Figure 25. Timing of 16-Bit Multiplexed Address/Data Bus, CRRWR = 1 (PSD3X2/3X3/3X4R) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input 15 32 STABLE INPUT 6 Multiplexed (49) Inputs 6 14 STABLE INPUT 14 WRITE CYCLE 32 BHE/PSEN as BHE A0/AD0A15/AD15 Active High AS Active Low AS RD/E/DS as E 5 RD/E/DS as DS 33 WR/VPP or R/W as R/W 18 Any of PA0-PA7 as I/O Pin Any of PB0-PB7 as I/O Pin 23 Any of PA0-PA7 Pins as Address Outputs See referenced notes on page 2-61. 10 ADDRESS A 2 1 3 DATA VALID 9 2 ADDRESS B 3 16 1 35 DATA IN 17 4 8 13 34 35 33 34 12 36 12 13 19 INPUT 20 OUTPUT INPUT 23 ADDRESS A ADDRESS B OUTPUT 2-48 PSD3XX Family Figure 26. Timing of 8-Bit Non-Multiplexed Address/Data Bus, CRRWR = 0 (PSD3X1) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input 15 WRITE CYCLE 32 STABLE INPUT 6 STABLE INPUT 14 STABLE INPUT 32 32 A0/AD0A15/AD15 as A0-A15 PC0-PC2, CSI/A19 as Multiplexed Inputs PA0-PA7 2 Active High ALE Active Low ALE 1 3 STABLE INPUT 6 10 14 DATA IN DATA VALID 9 2 3 16 17 1 4 8 12 13 11 RD/E as RD 36 12A 13 WR/VPP or R/W as WR 5 18 19 INPUT 20 Any of PB0-PB7 as I/O Pin OUTPUT See referenced notes on page 2-61. 2-49 PSD3XX Family Figure 27. Timing of 8-Bit Non-Multiplexed Address/Data Bus, CRRWR = 0 (PSD3X2/3X3/3X4R) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input A0/AD0A15/AD15 as A0-A15 Multiplexed Inputs (49) WRITE CYCLE 32 15 STABLE INPUT 6 STABLE INPUT 32 STABLE INPUT 14 STABLE INPUT 32 6 10 14 DATA IN PA0-PA7 2 Active High ALE Active Low ALE 1 4 8 12 RD/E/DS as RD 3 DATA VALID 9 2 3 16 17 1 13 11 36 12A 13 WR/VPP or R/W as WR 5 18 19 INPUT 20 Any of PB0-PB7 as I/O Pin OUTPUT See referenced notes on page 2-61. 2-50 PSD3XX Family Figure 28. Timing of 8-Bit Non-Multiplexed Address/Data Bus, CRRWR = 1 (PSD3X1) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input A0/AD0A15/AD15 as A0-A15 15 WRITE CYCLE 32 STABLE INPUT 6 STABLE INPUT 32 STABLE INPUT 14 STABLE INPUT 32 PC0-PC2, CSI/A19 as Multiplexed Inputs PA0-PA7 2 Active High ALE Active Low ALE RD/E as E 1 3 6 10 14 DATA IN DATA VALID 9 2 3 16 1 35 35 17 4 12 33 13 34 36 34 33 12 13 8 WR/VPP or R/W as R/W 18 Any of PB0-PB7 as I/O Pin INPUT 19 20 OUTPUT See referenced notes on page 2-61. 2-51 PSD3XX Family Figure 29. Timing of 8-Bit Non-Multiplexed Address/Data Bus, CRRWR = 1 (PSD3X2/3X3/3X4R) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input A0/AD0A15/AD15 as A0-A15 Multiplexed (49) Inputs 6 10 14 DATA IN 15 WRITE CYCLE 32 STABLE INPUT 6 STABLE INPUT 32 STABLE INPUT 14 STABLE INPUT 32 PA0-PA7 2 Active High ALE Active Low ALE RD/E/DS as E 5 RD/E/DS as DS 12 33 1 3 DATA VALID 9 2 3 16 1 35 17 4 8 13 34 36 35 33 12 34 13 WR/VPP or R/W as R/W 18 Any of PB0-PB7 as I/O Pin INPUT 19 20 OUTPUT See referenced notes on page 2-61. 2-52 PSD3XX Family Figure 30. Timing of 16-Bit Non-Multiplexed Address/Data Bus, CRRWR = 0 (PSD3X1) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input A0/AD0A15/AD15 as A0-A15 PC0-PC2, CSI/A19 as Multiplexed Inputs BHE/PSEN as BHE 15 WRITE CYCLE 32 STABLE INPUT 6 STABLE INPUT 32 STABLE INPUT 14 STABLE INPUT 32 14 6 DATA IN DATA VALID 9 17 PA0-PA7 (Low Byte) PB0-PB7 (High Byte) 2 Active High ALE Active Low ALE 1 4 3 DATA VALID 9 10 2 3 16 DATA IN 1 8 12 13 11 RD/E as RD 36 13 12A WR/VPP or R/W as WR See referenced notes on page 2-61. 2-53 PSD3XX Family Figure 31. Timing of 16-Bit Non-Multiplexed Address/Data Bus, CRRWR = 0 (PSD3X2/3X3/3X4R) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input A0/AD0A15/AD15 as A0-A15 15 WRITE CYCLE 32 STABLE INPUT 6 STABLE INPUT 32 STABLE INPUT 14 STABLE INPUT 32 Multiplexed (49) Inputs 14 BHE/PSEN as BHE 6 DATA IN DATA VALID 9 17 PA0-PA7 (Low Byte) PB0-PB7 (High Byte) 2 Active High ALE Active Low ALE 1 4 3 DATA VALID 2 10 3 16 DATA IN 1 8 12 13 11 RD/E/DS as RD 5 WR/VPP or R/W as WR 36 12A 13 See referenced notes on page 2-61. 2-54 PSD3XX Family Figure 32. Timing of 16-Bit Non-Multiplexed Address/Data Bus, CRRWR = 1 (PSD3X1) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input A0/AD0A15/AD15 as A0-A15 PC0-PC2, CSI/A19 as Multiplexed Inputs BHE/PSEN as BHE 6 PA0-PA7 (Low Byte) DATA IN DATA VALID 9 PB0-PB7 (High Byte) 2 Active High AS Active Low AS 1 4 35 8 33 RD/E as E 12 WR/VPP or R/W as R/W 13 34 36 33 13 34 1 35 3 DATA IN 15 WRITE CYCLE 32 STABLE INPUT 6 STABLE INPUT 32 STABLE INPUT 14 STABLE INPUT 32 14 DATA VALID 10 2 3 16 17 See referenced notes on page 2-61. 2-55 PSD3XX Family Figure 33. Timing of 16-Bit Non-Multiplexed Address/Data Bus, CRRWR = 1 (PSD3X2/3X3/3X4R) READ CYCLE 32 CSI/A19 as CSI 7 Direct (48) PAD Input A0/AD0A15/AD15 as A0-A15 15 WRITE CYCLE 32 STABLE INPUT 6 STABLE INPUT 32 STABLE INPUT 14 STABLE INPUT 32 Multiplexed Inputs (49) 14 BHE/PSEN as BHE 6 PA0-PA7 (Low Byte) DATA IN DATA VALID 9 PB0-PB7 (High Byte) 2 Active High AS Active Low AS 1 4 35 8 33 RD/E/DS as E 5 RD/E/DS as DS 12 12 13 34 36 33 1 35 13 34 3 DATA IN DATA VALID 10 2 3 16 17 WR/VPP or R/W as R/W See referenced notes on page 2-61. 2-56 PSD3XX Family Figure 34. Chip-Select Output Timing (PSD30X) 30 A19/CSI as CSI Direct PAD (48) Input Multiplexed (49) PAD Inputs 2 ALE (Multiplexed Mode Only) or ALE (Multiplexed Mode Only) 21 CSOi (50,55) 3 31 INPUT STABLE 1 22 See referenced notes on page 2-61. 2-57 PSD3XX Family Figure 35. Port A as AD0-AD7 Timing (Track Mode), CRRWR = 0 (PSD3X1) READ CYCLE 32 Direct PAD Input (48,51) WRITE CYCLE 32 STABLE INPUT 2 STABLE INPUT STABLE INPUT 2 STABLE INPUT 2 3 ADDRESS 25 26 DATA VALID 2 Multiplexed PAD Inputs (52,54) 3 ADDRESS WRITTEN DATA A0/AD0A7/AD7 32 ALE 1 1 or ALE 4 12 32 27 RD/E as RD 11 WR/VPP or R/W as WR PA0-PA7 23 CSOi (50,53) 12A 24 24 ADR OUT DATA IN 23 ADR OUT 28 DATA OUT 29 See referenced notes on page 2-61. 2-58 PSD3XX Family Figure 36. Port A as AD0-AD7 Timing (Track Mode), CRRWR = 0 (PSD3X2/3X3/3X4R) READ CYCLE 32 Direct PAD Input (48,51) WRITE CYCLE 32 STABLE INPUT 2 STABLE INPUT STABLE INPUT 2 STABLE INPUT 2 3 ADDRESS 25 26 DATA VALID 2 Multiplexed PAD Inputs (52,54) 3 ADDRESS WRITTEN DATA A0/AD0A7/AD7 32 ALE 1 1 or ALE 4 12 32 27 RD/E/DS as RD 11 WR/VPP or R/W as WR PA0-PA7 23 CSOi (50,53) 12A 24 24 ADR OUT DATA IN 23 ADR OUT 28 DATA OUT 29 See referenced notes on page 2-61. 2-59 PSD3XX Family Figure 37. Port A as AD0-AD7 Timing (Track Mode), CRRWR = 1 (PSD3X1) READ CYCLE 32 Direct PAD Input (48,51) WRITE CYCLE 32 STABLE INPUT STABLE INPUT 2 STABLE INPUT 2 3 ADDRESS 25 26 DATA VALID 2 Multiplexed PAD Inputs (52,54) STABLE INPUT 3 ADDRESS WRITTEN DATA A0/AD0A7/AD7 32 AS 1 1 35 12 33 RD/E as E 34 35 33 12 or AS WR/VPP or R/W as R/W 24 PA0-PA7 23 CSOi (50,53) 34 24 DATA IN 23 ADR OUT 28 27 DATA OUT ADR OUT 29 See referenced notes on page 2-61. 2-60 PSD3XX Family Figure 38. Port A as AD0-AD7 Timing (Track Mode), CRRWR = 1 (PSD3X2/3X3/3X4R) Direct PAD Input (48,51) READ CYCLE 32 STABLE INPUT 2 STABLE INPUT 2 3 ADDRESS 25 26 DATA VALID 2 WRITE CYCLE 32 STABLE INPUT Multiplexed PAD Inputs (52,54) STABLE INPUT 3 ADDRESS WRITTEN DATA A0/AD0A7/AD7 32 AS 1 1 35 12 33 RD/E/DS as E 34 RD/E/DS as DS 35 33 12 or AS WR/VPP or R/W as R/W 24 PA0-PA7 23 CSOi (50,53) 34 24 DATA IN 23 ADR OUT 28 27 DATA OUT ADR OUT 29 Notes for Timing Diagrams 48. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E/DS, WR or R/W, transparent PC0-PC2, ALE in non-multiplexed modes. 49. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS): A0/AD0-A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent PC0-PC2. 50. CSOi = any of the chip-select output signals coming through Port B (CS0-CS7) or through Port C (CS8-CS10). 51. CSADOUT1, which internally enables the address transfer to Port A, should be derived only from direct PAD input signals, otherwise the address propagation delay is slowed down. 52. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively, can be derived from any combination of direct PAD inputs and multiplexed PAD inputs. 53. The write operation signals are included in the CSOi expression. 54. Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE (or AS) in the multiplexed modes: A11/AD11-A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent PC0-PC2. 55. CSOi product terms can include any of the PAD input signals shown in Figure 3, except for reset and CSI. 2-61 PSD3XX Family Table 14. Pin Capacitance 56 Symbol CIN COUT CVPP Parameter Capacitance (for input pins only) Capacitance (for input/output pins) Capacitance (for WR/VPP or R/W/VPP) Conditions Typical 57 Max Unit VIN = 0 V VOUT = 0 V VPP = 0 V 4 8 18 6 12 25 pF pF pF NOTES: 56. This parameter is only sampled and is not 100% tested. 57. Typical values are for TA = 25C and nominal supply voltages. Figure 39. AC Testing Input/Output Waveform (PSD3XX Versions) 3.0V TEST POINT 0V 1.5V Figure 39a. AC Testing Input/Output Waveform (PSD3XXL Versions) 0.9VCC TEST POINT 0V 1.5V Figure 40. AC Testing Load Circuit (PSD3XX Versions) 2.01 V 195 DEVICE UNDER TEST CL = 30 pF (INCLUDING SCOPE AND JIG CAPACITANCE) Figure 40a. AC Testing Load Circuit (PSD3XXL Versions) 2.0 V 400 DEVICE UNDER TEST CL = 30 pF (INCLUDING SCOPE AND JIG CAPACITANCE) 2-62 PSD3XX Family Erasure and Programming To clear all locations of their programmed contents, expose the window packaged device to an ultra-violet light source. A dosage of 30 W second/cm 2 is required (40 W second/cm 2 for PSD3XXL versions). This dosage can be obtained with exposure to a wavelength of 2537 A and intensity of 12000 W/cm 2 for 40 to 45 minutes (50 to 60 minutes for PSD3XXL versions). The device should be about 1 inch from the source, and all filters should be removed from the UV light source prior to erasure. The PSD3XX and similar devices will erase with light sources having wavelengths shorter than 4000 A. Although the erasure times will be much longer than with UV sources at 2537 A, exposure to fluorescent light and sunlight eventually erases the device. For maximum system reliability, these sources should be avoided. If used in such an environment, the package window should be covered by an opaque substance. Upon delivery from WSI, or after each erasure, the PSD3XX device has all bits in the PAD and EPROM in the "1" or high state. The configuration bits are in the "0" or low state. The code, configuration, and PAD MAP data are loaded through the procedure of programming Information for programming the device is available directly from WSI. Please contact your local sales representative. 2-63 Programmable Peripheral PSD301 Field-Programmable Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A and PAD B) -- Total of 40 Product Terms and up to 12 Inputs and 24 Outputs -- Address Decoding up to 1 MB -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode Selectable 8 or 16 bit data bus width ALE and Reset polarity programmable Selectable modes for read and write control bus as RD/WR or R/W/E BHE pin for byte select in 16-bit mode PSEN pin for 8051 users t 256 Kbits of UV EPROM -- -- -- -- Configurable as 32K x 8 or as 16K x 16 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 4K x 8 or 2K x 16 70 ns EPROM access time, including input latches and PAD address decoding. t 16 Kbit Static RAM -- Configurable as 2K x 8 or as 1K x 16 -- 70 ns SRAM access time, including input latches and PAD address decoding t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t Built-In Security -- Locks the PSD301 and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCC and TQFP -- 52 Pin PQFP -- 44 Pin CPGA t Simple Menu-Driven Software: Configure the PSD301 on an IBM PC t Pin and Function Compatible with the PSD302 /302L, PSD303/303L and PSD304R/314RL 2-65 PSD3XX Family PSD301 Pin Assignments Pin Name BHE/PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 GND AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin CPGA Package A5 A4 B4 A3 B3 A2 B2 B1 C2 C1 D2 D1 E1 E2 F1 F2 G1 G2 H2 G3 H3 G4 H4 H5 G5 H6 G6 H7 G7 G8 F7 F8 E7 E8 D8 D7 C8 C7 B8 B7 A7 B6 A6 B5 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 52-Pin PQFP Package (Note 58) 46 47 48 49 50 51 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 25 28 29 30 31 32 33 34 35 36 37 38 41 42 43 44 45 NOTE: 58. Pins 1, 13, 14, 26, 27, 39, 40, and 52 are No Connect. 2-66 PSD3XX Family 2 WR/VPP or R/W 1 BHE/PSEN 43 A19/CSI PSD301 Package Information 3 RESET 6 PB5 5 PB6 42 PC2 41 PC1 PA3 18 PA2 19 PA1 20 PA0 21 RD/E 22 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 AD4/A4 27 (TOP VIEW) Figure 42. Drawing U1 - 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 40 WR/VPP or R/W 39 BHE/PSEN 37 A19/CSI 41 RESET 36 PC2 35 PC1 34 PC0 44 PB5 43 PB6 42 PB7 38 VCC AD5/A5 28 Figure 41. Drawing L4 - 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) OR Drawing J2 - 44 Pin Plastic Leaded Chip Carrier (PLDCC) without Window (Package Type J) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 AD15/A15 38 AD14/A14 37 AD13/A13 36 AD12/A12 35 AD11/A11 34 GND 33 AD10/A10 32 AD9/A9 31 AD8/A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 33 AD15/A15 32 AD14/A14 31 AD13/A13 30 AD12/A12 29 AD11/A11 28 GND 27 AD10/A10 26 AD9/A9 25 AD8/A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) AD5/A5 22 2-67 PSD3XX Family 47 WR/VPP or R/W 46 BHE/PSEN 44 A19/CSI PSD301 Package Information 48 RESET 51 PB5 50 PB6 49 PB7 52 NC 43 PC2 42 PC1 41 PC0 45 VCC Figure 43. Drawing Q2 - 52 Pin PQFP (Package Type Q) NC PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 1 2 3 4 5 6 7 8 9 40 NC 39 NC 38 AD15/A15 37 AD14/A14 36 AD13/A13 35 AD12/A12 34 AD11/A11 33 GND 32 AD10/A10 31 AD9/A9 30 AD8/A8 29 AD7/A7 28 AD6/A6 27 NC PA6 10 PA5 11 PA4 12 NC 13 NC 14 PA3 15 PA2 16 PA1 17 PA0 18 RD/E 19 AD0/A0 20 AD1/A1 21 AD2/A2 22 AD3/A3 23 AD4/A4 24 AD5/A5 25 (TOP VIEW) Figure 44. Drawing X2 - 44 Pin CPGA (Package Type X) 1 A B C D E F G H 2 3 4 5 6 7 8 (TOP VIEW, THROUGH PACKAGE) 2-68 NC 26 Programmable Peripheral PSD311 Field-Programmable Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A and PAD B) -- Total of 40 Product Terms and up to 12 Inputs and 24 Outputs -- Address Decoding up to 1 MB -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode 8-bit data bus width ALE and Reset polarity programmable Selectable modes for read and write control bus as RD/WR or R/W/E PSEN pin for 8051 users t 256 Kbits of UV EPROM -- -- -- -- Configurable as 32K x 8 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 4K x 8 70 ns EPROM access time, including input latches and PAD address decoding. t 16 Kbit Static RAM -- Configurable as 2K x 8 -- 70 ns SRAM access time, including input latches and PAD address decoding t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t Built-In Security -- Locks the PSD311 and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCCand TQFP -- 52 Pin PQFP t Simple Menu-Driven Software: Configure the PSD311 on an IBM PC t Pin and Function Compatible with the PSD312 /312L, PSD313/313L and PSD314R/314RL 2-69 PSD3XX Family PSD311 Pin Assignments Pin Name PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 A8 A9 A10 GND A11 A12 A13 A14 A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 52-Pin PQFP Package (Note 59) 46 47 48 49 50 51 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 25 28 29 30 31 32 33 34 35 36 37 38 41 42 43 44 45 NOTE: 59. Pins 1, 13, 14, 26, 27, 39, 40, and 52 are No Connect. 2-70 PSD3XX Family 2 WR/VPP or R/W 43 A19/CSI PSD311 Package Information 3 RESET 6 PB5 5 PB6 1 PSEN 42 PC2 41 PC1 PA3 18 PA2 19 PA1 20 PA0 21 RD/E 22 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 AD4/A4 27 (TOP VIEW) Figure 46. Drawing U1 - 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 40 WR/VPP or R/W 39 PSEN 38 VCC 37 A19/CSI 41 RESET 36 PC2 35 PC1 34 PC0 44 PB5 43 PB6 42 PB7 AD5/A5 28 Figure 45. Drawing L4 - 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) OR Drawing J2 - 44 Pin Plastic Leaded Chip Carrier (PLDCC) without Window (Package Type J) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 A15 38 A14 37 A13 36 A12 35 A11 34 GND 33 A10 32 A9 31 A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 33 A15 32 A14 31 A13 30 A12 29 A11 28 GND 27 A10 26 A9 25 A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) AD5/A5 22 2-71 PSD3XX Family 47 WR/VPP or R/W PSD311 Package Information 48 RESET Figure 47. Drawing Q2 - 52 Pin PQFP (Package Type Q) NC PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 1 2 3 4 5 6 7 8 9 44 A19/CSI 46 PSEN 51 PB5 50 PB6 49 PB7 43 PC2 42 PC1 41 PC0 45 VCC 52 NC 40 NC 39 NC 38 A15 37 A14 36 A13 35 A12 34 A11 33 GND 32 A10 31 A9 30 A8 29 AD7/A7 28 AD6/A6 27 NC PA6 10 PA5 11 PA4 12 NC 13 RD/E 19 NC 14 PA3 15 PA2 16 PA1 17 PA0 18 AD0/A0 20 AD1/A1 21 AD2/A2 22 AD3/A3 23 AD4/A4 24 AD5/A5 25 (TOP VIEW) 2-72 NC 26 Programmable Peripheral PSD302 Field-Programmable Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A & PAD B) -- Total of 40 Product Terms and up to 16 Inputs and 24 Outputs -- Direct Address Decoding up to 1 Meg address space and up to 16 Meg with paging -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode Selectable 8 or 16 bit data bus width ALE and Reset polarity programmable Selectable modes for read and write control bus as RD/WR, R/W/E, or R/W/DS BHE pin for byte select in 16-bit mode PSEN pin for 8051 users t Built-In Page Logic -- To Expand the Address Space of Microcontrollers with Limited Address Space Capabilities -- Up to 16 pages t 512 Kbits of UV EPROM -- -- -- -- Configurable as 64K x 8 or as 32K x 16 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 8K x 8 or 4K x 16 70 ns EPROM access time, including input latches and PAD address decoding. t 16 Kbit Static RAM -- Configurable as 2K x 8 or as 1K x 16 -- 70 ns SRAM access time, including input latches and PAD address decoding t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t CMiser-Bit -- Programmable option to further reduce power consumption t Built-In Security -- Locks the PSD302 and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCC and TQFP -- 52 Pin PQFP -- 44 Pin CPGA t Simple Menu-Driven Software: Configure the PSD302 on an IBM PC t Pin and Function Compatible with the PSD301/301L, PSD303/303L and PSD304R/304RL 2-73 PSD3XX Family PSD302 Pin Assignments Pin Name BHE/PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E/DS AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 GND AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin CPGA Package A5 A4 B4 A3 B3 A2 B2 B1 C2 C1 D2 D1 E1 E2 F1 F2 G1 G2 H2 G3 H3 G4 H4 H5 G5 H6 G6 H7 G7 G8 F7 F8 E7 E8 D8 D7 C8 C7 B8 B7 A7 B6 A6 B5 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 52-Pin PQFP Package (Note 60) 46 47 48 49 50 51 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 25 28 29 30 31 32 33 34 35 36 37 38 41 42 43 44 45 NOTE: 60. Pins 1, 13, 14, 26, 27, 39, 40, and 52 are No Connect. 2-74 PSD3XX Family 2 WR/VPP or R/W 1 BHE/PSEN 43 A19/CSI 3 RESET PSD302 Package Information 6 PB5 5 PB6 42 PC2 41 PC1 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 AD4/A4 27 (TOP VIEW) Figure 49. Drawing U1 - 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 40 WR/VPP or R/W 39 BHE/PSEN 37 A19/CSI 41 RESET 36 PC2 35 PC1 34 PC0 44 PB5 43 PB6 42 PB7 38 VCC AD5/A5 28 Figure 48. Drawing L4 - 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) OR Drawing J2 - 44 Pin Plastic Leaded Chip Carrier (PLDCC) without Window (Package Type J) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 AD15/A15 38 AD14/A14 37 AD13/A13 36 AD12/A12 35 AD11/A11 34 GND 33 AD10/A10 32 AD9/A9 31 AD8/A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 33 AD15/A15 32 AD14/A14 31 AD13/A13 30 AD12/A12 29 AD11/A11 28 GND 27 AD10/A10 26 AD9/A9 25 AD8/A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E/DS 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) AD5/A5 22 2-75 PSD3XX Family 47 WR/VPP or R/W 46 BHE/PSEN 44 A19/CSI PSD302 Package Information 48 RESET 51 PB5 50 PB6 49 PB7 52 NC 43 PC2 42 PC1 41 PC0 45 VCC Figure 50. Drawing Q2 - 52 Pin PQFP (Package Type Q) NC PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 1 2 3 4 5 6 7 8 9 40 NC 39 NC 38 AD15/A15 37 AD14/A14 36 AD13/A13 35 AD12/A12 34 AD11/A11 33 GND 32 AD10/A10 31 AD9/A9 30 AD8/A8 29 AD7/A7 28 AD6/A6 27 NC PA6 10 PA5 11 PA4 12 NC 13 RD/E/DS 19 NC 14 PA3 15 PA2 16 PA1 17 PA0 18 AD0/A0 20 AD1/A1 21 AD2/A2 22 AD3/A3 23 AD4/A4 24 7 AD5/A5 25 8 (TOP VIEW) Figure 51. Drawing X2 - 44 Pin CPGA (Package Type X) A B C D E F G H 1 2 3 4 5 6 (TOP VIEW, THROUGH PACKAGE) 2-76 NC 26 Programmable Peripheral PSD312 Field-Programmable Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A & PAD B) -- Total of 40 Product Terms and up to 16 Inputs and 24 Outputs -- Direct Address Decoding up to 1 Meg address space and up to 16 Meg with paging -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode 8-bit data bus width ALE and Reset polarity programmable Selectable modes for read and write control bus as RD/WR, R/W/E, or R/W/DS PSEN pin for 8051 users t Built-In Page Logic -- To Expand the Address Space of Microcontrollers with Limited Address Space Capabilities -- Up to 16 pages t 512 Kbits of UV EPROM -- -- -- -- Configured as 64K x 8 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 8K x 8 70 ns EPROM access time, including input latches and PAD address decoding. t 16 Kbit Static RAM -- Configured as 2K x 8 -- 70 ns SRAM access time, including input latches and PAD address decoding t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t CMiser-Bit -- Programmable option to further reduce power consumption t Built-In Security -- Locks the PSD312 and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCC and TQFP -- 52 Pin PQFP t Simple Menu-Driven Software: Configure the PSD312 on an IBM PC t Pin and Function Compatible with the PSD311/311L, PSD313/313L and PSD314R/314RL 2-77 PSD3XX Family PSD312 Pin Assignments Pin Name PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E/DS AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 A8 A9 A10 GND A11 A12 A13 A14 A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 52-Pin PQFP Package (Note 61) 46 47 48 49 50 51 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 25 28 29 30 31 32 33 34 35 36 37 38 41 42 43 44 45 NOTE: 61. Pins 1, 13, 14, 26, 27, 39, 40, and 52 are No Connect. 2-78 PSD3XX Family 2 WR/VPP or R/W 43 A19/CSI 3 RESET 1 PSEN PSD312 Package Information 6 PB5 5 PB6 42 PC2 41 PC1 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 AD4/A4 27 (TOP VIEW) Figure 53. Drawing U1 - 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 40 WR/VPP or R/W 37 A19/CSI 41 RESET 39 PSEN 36 PC2 35 PC1 34 PC0 44 PB5 43 PB6 42 PB7 38 VCC AD5/A5 28 Figure 52. Drawing L4 - 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) OR Drawing J2 - 44 Pin Plastic Leaded Chip Carrier (PLDCC) without Window (Package Type J) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 A15 38 A14 37 A13 36 A12 35 A11 34 GND 33 A10 32 A9 31 A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 33 A15 32 A14 31 A13 30 A12 29 A11 28 GND 27 A10 26 A9 25 A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E/DS 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) AD5/A5 22 2-79 PSD3XX Family 47 WR/VPP or R/W PSD312 Package Information 48 RESET Figure 54. Drawing Q2 - 52 Pin PQFP (Package Type Q) NC PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 1 2 3 4 5 6 7 8 9 44 A19/CSI 46 PSEN 51 PB5 50 PB6 49 PB7 43 PC2 42 PC1 41 PC0 45 VCC 52 NC 40 NC 39 NC 38 A15 37 A14 36 A13 35 A12 34 A11 33 GND 32 A10 31 A9 30 A8 29 AD7/A7 28 AD6/A6 27 NC PA6 10 PA5 11 PA4 12 NC 13 RD/E/DS 19 NC 14 PA3 15 PA2 16 PA1 17 PA0 18 AD0/A0 20 AD1/A1 21 AD2/A2 22 AD3/A3 23 AD4/A4 24 AD5/A5 25 (TOP VIEW) 2-80 NC 26 Programmable Peripheral PSD303 Field-Programmable Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A & PAD B) -- Total of 40 Product Terms and up to 16 Inputs and 24 Outputs -- Direct Address Decoding up to 1 Meg address space and up to 16 Meg with paging -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode Selectable 8 or 16 bit data bus width ALE and Reset polarity programmable Selectable modes for read and write control bus as RD/WR, R/W/E, or R/W/DS BHE pin for byte select in 16-bit mode PSEN pin for 8051 users t Built-In Page Logic -- To Expand the Address Space of Microcontrollers with Limited Address Space Capabilities -- Up to 16 pages t 1 M bit of UV EPROM -- -- -- -- Configurable as 128K x 8 or as 64K x 16 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 16K x 8 or 8K x 16 70 ns EPROM access time, including input latches and PAD address decoding. t 16 Kbit Static RAM -- Configurable as 2K x 8 or as 1K x 16 -- 70 ns SRAM access time, including input latches and PAD address decoding t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t Built-In Security -- Locks the PSD303 and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCC and TQFP -- 44 Pin CPGA t Simple Menu-Driven Software: Configure the PSD303 on an IBM PC t Pin and Function Compatible with the PSD301/301L, PSD302/302L and PSD304R/314RL 2-81 PSD3XX Family PSD303 Pin Assignments Pin Name BHE/PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E/DS AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 GND AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin CPGA Package A5 A4 B4 A3 B3 A2 B2 B1 C2 C1 D2 D1 E1 E2 F1 F2 G1 G2 H2 G3 H3 G4 H4 H5 G5 H6 G6 H7 G7 G8 F7 F8 E7 E8 D8 D7 C8 C7 B8 B7 A7 B6 A6 B5 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 2-82 PSD3XX Family 2 WR/VPP or R/W 1 BHE/PSEN 43 A19/CSI 3 RESET PSD303 Package Information 6 PB5 5 PB6 42 PC2 41 PC1 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 AD4/A4 27 (TOP VIEW) Figure 56. Drawing U1 - 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 40 WR/VPP or R/W 39 BHE/PSEN 38 VCC 37 A19/CSI 41 RESET 36 PC2 35 PC1 34 PC0 44 PB5 43 PB6 42 PB7 AD5/A5 28 Figure 55. Drawing L4 - 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) OR Drawing J2 - 44 Pin Plastic Leaded Chip Carrier (PLDCC) without Window (Package Type J) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 AD15/A15 38 AD14/A14 37 AD13/A13 36 AD12/A12 35 AD11/A11 34 GND 33 AD10/A10 32 AD9/A9 31 AD8/A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 33 AD15/A15 32 AD14/A14 31 AD13/A13 30 AD12/A12 29 AD11/A11 28 GND 27 AD10/A10 26 AD9/A9 25 AD8/A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E/DS 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) AD5/A5 22 2-83 PSD3XX Family PSD303 Package Information 1 2 3 4 5 6 7 8 Figure 57. Drawing X2 - 44 Pin CPGA (Package Type X) A B C D E F G H (TOP VIEW, THROUGH PACKAGE) 2-84 Programmable Peripheral PSD313 Field-Programmable Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A & PAD B) -- Total of 40 Product Terms and up to 16 Inputs and 24 Outputs -- Direct Address Decoding up to 1 Meg address space and up to 16 Meg with paging -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode 8-bit data bus width ALE and Reset polarity programmable Selectable modes for read and write control bus as RD/WR, R/W/E, or R/W/DS PSEN pin for 8051 users t Built-In Page Logic -- To Expand the Address Space of Microcontrollers with Limited Address Space Capabilities -- Up to 16 pages t 1 M bit of UV EPROM -- -- -- -- Configurable as 128K x 8 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 16K x 8 70 ns EPROM access time, including input latches and PAD address decoding. t 16 Kbit Static RAM -- Configurable as 2K x 8 -- 70 ns SRAM access time, including input latches and PAD address decoding t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t Built-In Security -- Locks the PSD313 and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCC and TQFP -- 52 Pin PQFP t Simple Menu-Driven Software: Configure the PSD313 on an IBM PC t Pin and Function Compatible with the PSD311/311L, PSD312/312L and PSD314R/314RL 2-85 PSD3XX Family PSD313 Pin Assignments Pin Name PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E/DS AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 A8 A9 A10 GND A11 A12 A13 A14 A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 52-Pin PQFP Package (Note 62) 46 47 48 49 50 51 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 25 28 29 30 31 32 33 34 35 36 37 38 41 42 43 44 45 NOTE: 62. Pins 1, 13, 14, 26, 27, 39, 40, and 52 are No Connect. 2-86 PSD3XX Family 2 WR/VPP or R/W 43 A19/CSI 3 RESET PSD313 Package Information 6 PB5 5 PB6 1 PSEN 42 PC2 41 PC1 Figure 58. Drawing L4 - 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) OR Drawing J2 - 44 Pin Plastic Leaded Chip Carrier (PLDCC) without Window (Package Type J) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 A15 38 A14 37 A13 36 A12 35 A11 34 GND 33 A10 32 A9 31 A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 36 PC2 AD4/A4 27 35 PC1 (TOP VIEW) Figure 59. Drawing U1 - 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 40 WR/VPP or R/W 37 A19/CSI 41 RESET 39 PSEN 34 PC0 44 PB5 43 PB6 42 PB7 38 VCC AD5/A5 28 33 A15 32 A14 31 A13 30 A12 29 A11 28 GND 27 A10 26 A9 25 A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E/DS 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) AD5/A5 22 2-87 PSD3XX Family 47 WR/VPP or R/W 44 A19/CSI 48 RESET 46 PSEN PSD313 Package Information 51 PB5 50 PB6 49 PB7 52 NC 43 PC2 42 PC1 41 PC0 45 VCC Figure 60. Drawing Q2 - 52 Pin PQFP (Package Type Q) 40 NC NC PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 1 2 3 4 5 6 7 8 9 39 NC 38 A15 37 A14 36 A13 35 A12 34 A11 33 GND 32 A10 31 A9 30 A8 29 AD7/A7 28 AD6/A6 27 NC PA6 10 PA5 11 PA4 12 NC 13 NC 14 PA3 15 PA2 16 PA1 17 PA0 18 AD0/A0 20 AD1/A1 21 AD2/A2 22 AD3/A3 23 AD4/A4 24 AD5/A5 25 (TOP VIEW) 2-88 RD/E/DS 19 NC 26 Programmable Peripheral PSD304R Field-Programmable Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A & PAD B) -- Total of 40 Product Terms and up to 16 Inputs and 24 Outputs -- Direct Address Decoding up to 1 Meg address space and up to 16 Meg with paging -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode Selectable 8 or 16 bit data bus width ALE and Reset polarity programmable Selectable modes for read and write control bus as RD/WR, R/W/E, or R/W/DS BHE pin for byte select in 16-bit mode PSEN pin for 8051 users t Built-In Page Logic -- To Expand the Address Space of Microcontrollers with Limited Address Space Capabilities -- Up to 16 pages t 2 M bit of UV EPROM -- -- -- -- Configurable as 256K x 8 or as 128K x 16 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 32K x 8 or 16K x 16 120 ns EPROM access time, including input latches and PAD address decoding. t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t Built-In Security -- Locks the PSD304R and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCC and TQFP -- 44 Pin CPGA t Simple Menu-Driven Software: Configure the PSD304R on an IBM PC t Pin and Function Compatible with the PSD301/301L, PSD302/302L and PSD303/303L 2-89 PSD3XX Family PSD304R Pin Assignments Pin Name BHE/PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E/DS AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 GND AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin CPGA Package A5 A4 B4 A3 B3 A2 B2 B1 C2 C1 D2 D1 E1 E2 F1 F2 G1 G2 H2 G3 H3 G4 H4 H5 G5 H6 G6 H7 G7 G8 F7 F8 E7 E8 D8 D7 C8 C7 B8 B7 A7 B6 A6 B5 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 2-90 PSD3XX Family 2 WR/VPP or R/W 1 BHE/PSEN 43 A19/CSI 3 RESET PSD304R Package Information 6 PB5 5 PB6 42 PC2 41 PC1 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 AD4/A4 27 (TOP VIEW) Figure 62. Drawing U1 - 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 40 WR/VPP or R/W 39 BHE/PSEN 38 VCC 37 A19/CSI 41 RESET 36 PC2 35 PC1 34 PC0 44 PB5 43 PB6 42 PB7 AD5/A5 28 Figure 61. Drawing L4 - 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) OR Drawing J2 - 44 Pin Plastic Leaded Chip Carrier (PLDCC) without Window (Package Type J) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 AD15/A15 38 AD14/A14 37 AD13/A13 36 AD12/A12 35 AD11/A11 34 GND 33 AD10/A10 32 AD9/A9 31 AD8/A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 33 AD15/A15 32 AD14/A14 31 AD13/A13 30 AD12/A12 29 AD11/A11 28 GND 27 AD10/A10 26 AD9/A9 25 AD8/A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E/DS 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) AD5/A5 22 2-91 PSD3XX Family PSD304R Package Information 1 2 3 4 5 6 7 8 Figure 63. Drawing X2 - 44 Pin CPGA (Package Type X) A B C D E F G H (TOP VIEW, THROUGH PACKAGE) 2-92 Programmable Peripheral PSD314R Field-Programmable Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A & PAD B) -- Total of 40 Product Terms and up to 16 Inputs and 24 Outputs -- Direct Address Decoding up to 1 Meg address space and up to 16 Meg with paging -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode 8-bit data bus width ALE and Reset polarity programmable Selectable modes for read and write control bus as RD/WR, R/W/E, or R/W/DS PSEN pin for 8051 users t Built-In Page Logic -- To Expand the Address Space of Microcontrollers with Limited Address Space Capabilities -- Up to 16 pages t 2 M bit of UV EPROM -- -- -- -- Configurable as 256K x 8 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 32K x 8 120 ns EPROM access time, including input latches and PAD address decoding. t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t Built-In Security -- Locks the PSD314R and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCC and TQFP -- 52 Pin PQFP t Simple Menu-Driven Software: Configure the PSD314R on an IBM PC t Pin and Function Compatible with the PSD311/311L, PSD312/312L and PSD313/313L 2-93 PSD3XX Family PSD314R Pin Assignments Pin Name PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E/DS AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 A8 A9 A10 GND A11 A12 A13 A14 A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 52-Pin PQFP Package (Note 63) 46 47 48 49 50 51 2 3 4 5 6 7 8 9 10 11 12 15 16 17 18 19 20 21 22 23 24 25 28 29 30 31 32 33 34 35 36 37 38 41 42 43 44 45 NOTE: 63. Pins 1, 13, 14, 26, 27, 39, 40, and 52 are No Connect. 2-94 PSD3XX Family 2 WR/VPP or R/W 43 A19/CSI 3 RESET PSD314R Package Information 6 PB5 5 PB6 1 PSEN 42 PC2 41 PC1 Figure 64. Drawing L4 - 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) OR Drawing J2 - 44 Pin Plastic Leaded Chip Carrier (PLDCC) without Window (Package Type J) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 A15 38 A14 37 A13 36 A12 35 A11 34 GND 33 A10 32 A9 31 A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 36 PC2 AD4/A4 27 35 PC1 (TOP VIEW) Figure 65. Drawing U1 - 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 40 WR/VPP or R/W 37 A19/CSI 41 RESET 39 PSEN 34 PC0 44 PB5 43 PB6 42 PB7 38 VCC AD5/A5 28 33 A15 32 A14 31 A13 30 A12 29 A11 28 GND 27 A10 26 A9 25 A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E/DS 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) AD5/A5 22 2-95 PSD3XX Family 47 WR/VPP or R/W 44 A19/CSI 48 RESET 46 PSEN PSD314R Package Information 51 PB5 50 PB6 49 PB7 52 NC 43 PC2 42 PC1 41 PC0 45 VCC Figure 66. Drawing Q2 - 52 Pin PQFP (Package Type Q) 40 NC NC PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 1 2 3 4 5 6 7 8 9 39 NC 38 A15 37 A14 36 A13 35 A12 34 A11 33 GND 32 A10 31 A9 30 A8 29 AD7/A7 28 AD6/A6 27 NC PA6 10 PA5 11 PA4 12 NC 13 NC 14 PA3 15 PA2 16 PA1 17 PA0 18 AD0/A0 20 AD1/A1 21 AD2/A2 22 AD3/A3 23 AD4/A4 24 AD5/A5 25 (TOP VIEW) 2-96 RD/E/DS 19 NC 26 Programmable Peripheral PSD301L 3-Volt Single-Chip Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 3.0 to 5.5 Volt Operation t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A and PAD B) -- Total of 40 Product Terms and up to 12 Inputs and 24 Outputs -- Address Decoding up to 1 MB -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode Selectable 8 or 16 bit data bus width ALE polarity programmable Selectable modes for read and write control bus as RD/WR or R/W/E BHE pin for byte select in 16-bit mode PSEN pin for 8051 users t 256 Kbits of UV EPROM -- -- -- -- Configurable as 32K x 8 or as 16K x 16 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 4K x 8 or 2K x 16 150 ns EPROM access time, including input latches and PAD address decoding. t 16 Kbit Static RAM -- Configurable as 2K x 8 or as 1K x 16 -- 150 ns SRAM access time, including input latches and PAD address decoding t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t Built-In Security -- Locks the PSD301L and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCC and TQFP t Simple Menu-Driven Software: Configure the PSD301L on an IBM PC t Pin Compatible with the PSD3XX and PSD3XXL Series 2-97 PSD3XX Family PSD301L Pin Assignments Pin Name BHE/PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 GND AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 2-98 PSD3XX Family 2 WR/VPP or R/W 1 BHE/PSEN 43 A19/CSI 3 RESET PSD301L Package Information 6 PB5 5 PB6 42 PC2 41 PC1 Figure 67. Drawing L4 - 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 AD15/A15 38 AD/14/A14 37 AD13/A13 36 AD12/A12 35 AD11/A11 34 GND 33 AD10/A10 32 AD9/A9 31 AD8/A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 PA3 18 PA2 19 PA1 20 PA0 21 RD/E 22 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 42 PC2 AD4/A4 27 41 PC1 (TOP VIEW) 2 WR/VPP or R/W 1 BHE/PSEN 43 A19/CSI 3 RESET 40 PC0 44 VCC 6 PB5 5 PB6 4 PB7 Figure 68. Drawing J2 - 44 Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J) PB4 PB3 PB2 7 8 9 AD5/A5 28 39 AD15/A15 38 AD14/A14 37 AD13/A13 36 AD12/A12 35 AD11/A11 34 GND 33 AD10/A10 32 AD9/A9 31 AD8/A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 PA3 18 PA2 19 PA1 20 PA0 21 RD/E 22 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 AD4/A4 27 (TOP VIEW) AD5/A5 28 2-99 PSD3XX Family 40 WR/VPP or R/W 39 BHE/PSEN 38 VCC 37 A19/CSI PSD301L Package Information 41 RESET 44 PB5 43 PB6 36 PC2 35 PC1 Figure 69. Drawing U1 - 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) 34 PC0 42 PB7 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 33 AD15/A15 32 AD14/A14 31 AD13/A13 30 AD12/A12 29 AD11/A11 28 GND 27 AD10/A10 26 AD9/A9 25 AD8/A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) 2-100 AD5/A5 22 Programmable Peripheral PSD311L 3-Volt Single-Chip Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 3.0 to 5.5 Volt Operation t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A and PAD B) -- Total of 40 Product Terms and up to 12 Inputs and 24 Outputs -- Address Decoding up to 1 Meg address space -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode 8-bit data bus width ALE polarity programmable Selectable modes for read and write control bus as RD/WR or R/W/E PSEN pin for 8051 users t 256 Kbits of UV EPROM -- -- -- -- Organized as 32K x 8 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 4K x 8 150 ns EPROM access time, including input latches and PAD address decoding. t 16 Kbit Static RAM -- Organized as 2K x 8 -- 150 ns SRAM access time, including input latches and PAD address decoding t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t Built-In Security -- Locks the PSD311L and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCC and TQFP t Simple Menu-Driven Software: Configure the PSD311L on an IBM PC t Pin Compatible with the PSD3XX and PSD3XXL Series 2-101 PSD3XX Family PSD311L Pin Assignments Pin Name PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 A8 A9 A10 GND A11 A12 A13 A14 A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 2-102 PSD3XX Family 2 WR/VPP or R/W 43 A19/CSI 3 RESET PSD311L Package Information 6 PB5 5 PB6 1 PSEN 42 PC2 41 PC1 Figure 70. Drawing L4 -- 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 A15 38 A14 37 A13 36 A12 35 A11 34 GND 33 A10 32 A9 31 A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 RD/E 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 42 PC2 AD4/A4 27 41 PC1 (TOP VIEW) Figure 71. Drawing J2 -- 44 Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J) PB4 PB3 PB2 7 8 9 2 WR/VPP or R/W 43 A19/CSI 3 RESET 1 PSEN 40 PC0 44 VCC 6 PB5 5 PB6 4 PB7 AD5/A5 28 39 A15 38 A14 37 A13 36 A12 35 A11 34 GND 33 A10 32 A9 31 A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 PA3 18 PA2 19 PA1 20 PA0 21 RD/E 22 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 AD4/A4 27 (TOP VIEW) AD5/A5 28 2-103 PSD3XX Family 40 WR/VPP or R/W 38 VCC 37 A19/CSI 41 RESET PSD311L Package Information 44 PB5 43 PB6 39 PSEN 36 PC2 35 PC1 Figure 72. Drawing U1 -- 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) 34 PC0 42 PB7 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 33 A15 32 A14 31 A13 30 A12 29 A11 28 GND 27 A10 26 A9 25 A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) 2-104 AD5/A5 22 Programmable Peripheral PSD302L 3-Volt Single-Chip Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 3.0 to 5.5 Volt Operation t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A & PAD B) -- Total of 40 Product Terms and up to 16 Inputs and 24 Outputs -- Direct Address Decoding up to 1 Meg address space and up to 16 Meg with paging -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode Selectable 8 or 16 bit data bus width ALE polarity programmable Selectable modes for read and write control bus as RD/WR, R/W/E, or R/W/DS BHE pin for byte select in 16-bit mode PSEN pin for 8051 users t Built-In Page Logic -- To Expand the Address Space of Microcontrollers with Limited Address Space Capabilities -- Up to 16 pages t 512 Kbits of UV EPROM -- -- -- -- Configurable as 64K x 8 or as 32K x 16 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 8K x 8 or 4K x 16 150 ns EPROM access time, including input latches and PAD address decoding. t 16 Kbit Static RAM -- Configurable as 2K x 8 or as 1K x 16 -- 150 ns SRAM access time, including input latches and PAD address decoding t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t CMiser-Bit -- Programmable option to further reduce power consumption t Built-In Security -- Locks the PSD302L and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCC and TQFP t Simple Menu-Driven Software: Configure the PSD302L on an IBM PC t Pin and Functionally Compatible with the PSD3XX and PSD3XXL Series 2-105 PSD3XX Family PSD302L Pin Assignments Pin Name BHE/PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E/DS AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 GND AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 2-106 PSD3XX Family 2 WR/VPP or R/W 1 BHE/PSEN 43 A19/CSI 3 RESET PSD302L Package Information 6 PB5 5 PB6 42 PC2 41 PC1 Figure 73. Drawing L4 -- 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 AD15/A15 38 AD/14/A14 37 AD13/A13 36 AD12/A12 35 AD11/A11 34 GND 33 AD10/A10 32 AD9/A9 31 AD8/A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 42 PC2 AD4/A4 27 41 PC1 (TOP VIEW) Figure 74. Drawing J2 -- 44 Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J) PB4 PB3 PB2 7 8 9 2 WR/VPP or R/W 1 BHE/PSEN 43 A19/CSI 3 RESET 40 PC0 44 VCC 6 PB5 5 PB6 4 PB7 AD5/A5 28 39 AD15/A15 38 AD14/A14 37 AD13/A13 36 AD12/A12 35 AD11/A11 34 GND 33 AD10/A10 32 AD9/A9 31 AD8/A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 AD4/A4 27 (TOP VIEW) AD5/A5 28 2-107 PSD3XX Family 40 WR/VPP or R/W 39 BHE/PSEN 38 VCC 37 A19/CSI 41 RESET PSD302L Package Information 44 PB5 43 PB6 36 PC2 35 PC1 Figure 75. Drawing U1 - 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) 34 PC0 42 PB7 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 33 AD15/A15 32 AD14/A14 31 AD13/A13 30 AD12/A12 29 AD11/A11 28 GND 27 AD10/A10 26 AD9/A9 25 AD8/A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E/DS 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) 2-108 AD5/A5 22 Programmable Peripheral PSD312L 3-Volt Single-Chip Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 3.0 to 5.5 Volt Operation t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A & PAD B) -- Total of 40 Product Terms and up to 16 Inputs and 24 Outputs -- Direct Address Decoding up to 1 Meg address space and up to 16 Meg with paging -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode 8-bit data bus width ALE polarity programmable Selectable modes for read and write control bus as RD/WR, R/W/E, or R/W/DS PSEN pin for 8051 users t Built-In Page Logic -- To Expand the Address Space of Microcontrollers with Limited Address Space Capabilities -- Up to 16 pages t 512 Kbits of UV EPROM -- -- -- -- Configured as 64K x 8 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 8K x 8 150 ns EPROM access time, including input latches and PAD address decoding. t 16 Kbit Static RAM -- Configured as 2K x 8 -- 150 ns SRAM access time, including input latches and PAD address decoding t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t CMiser-Bit -- Programmable option to further reduce power consumption t Built-In Security -- Locks the PSD312L and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCC and TQFP t Simple Menu-Driven Software: Configure the PSD312L on an IBM PC t Pin and Functionally Compatible with the PSD3XX and PSD3XXL Series. 2-109 PSD3XX Family PSD312L Pin Assignments Pin Name PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E/DS AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 A8 A9 A10 GND A11 A12 A13 A14 A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 2-110 PSD3XX Family 2 WR/VPP or R/W 43 A19/CSI 3 RESET PSD312L Package Information 6 PB5 5 PB6 1 PSEN 42 PC2 41 PC1 Figure 76. Drawing L4 -- 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 A15 38 A14 37 A13 36 A12 35 A11 34 GND 33 A10 32 A9 31 A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 42 PC2 AD4/A4 27 41 PC1 (TOP VIEW) Figure 77. Drawing J2 -- 44-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J) PB4 PB3 PB2 7 8 9 2 WR/VPP or R/W 43 A19/CSI 3 RESET 1 PSEN 40 PC0 44 VCC 6 PB5 5 PB6 4 PB7 AD5/A5 28 39 A15 38 A14 37 A13 36 A12 35 A11 34 GND 33 A10 32 A9 31 A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 AD4/A4 27 (TOP VIEW) AD5/A5 28 2-111 PSD3XX Family 40 WR/VPP or R/W 37 A19/CSI 41 RESET PSD312L Package Information 44 PB5 43 PB6 42 PB7 39 PSEN 36 PC2 35 PC1 Figure 78. Drawing U1 - 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) 34 PC0 38 VCC PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 33 A15 32 A14 31 A13 30 A12 29 A11 28 GND 27 A10 26 A9 25 A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E/DS 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) 2-112 AD5/A5 22 Programmable Peripheral PSD303L 3-Volt Single-Chip Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 3.0 to 5.5 Volt Operation t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A & PAD B) -- Total of 40 Product Terms and up to 16 Inputs and 24 Outputs -- Direct Address Decoding up to 1 Meg address space and up to 16 Meg with paging -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode Selectable 8 or 16 bit data bus width ALE polarity programmable Selectable modes for read and write control bus as RD/WR, R/W/E, or R/W/DS BHE pin for byte select in 16-bit mode PSEN pin for 8051 users t Built-In Page Logic -- To Expand the Address Space of Microcontrollers with Limited Address Space Capabilities -- Up to 16 pages t 1M bit of UV EPROM -- -- -- -- Configurable as 128K x 8 or as 64K x 16 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 16K x 8 or 8K x 16 150 ns EPROM access time, including input latches and PAD address decoding. t 16 Kbit Static RAM -- Configurable as 2K x 8 or as 1K x 16 -- 150 ns SRAM access time, including input latches and PAD address decoding t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t CMiser-Bit -- Programmable option to further reduce power consumption t Built-In Security -- Locks the PSD303L and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCC and TQFP t Simple Menu-Driven Software: Configure the PSD303L on an IBM PC t Pin and Functionally Compatible with the PSD3XX and PSD3XXL Series 2-113 PSD3XX Family PSD303L Pin Assignments Pin Name BHE/PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E/DS AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 GND AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 2-114 PSDXX Family 2 WR/VPP or R/W 1 BHE/PSEN 43 A19/CSI 3 RESET PSD303L Package Information 6 PB5 5 PB6 42 PC2 41 PC1 Figure 79. Drawing L4 -- 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 AD15/A15 38 AD/14/A14 37 AD13/A13 36 AD12/A12 35 AD11/A11 34 GND 33 AD10/A10 32 AD9/A9 31 AD8/A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 42 PC2 AD4/A4 27 41 PC1 (TOP VIEW) Figure 80. Drawing J2 -- 44 Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J) PB4 PB3 PB2 7 8 9 2 WR/VPP or R/W 1 BHE/PSEN 43 A19/CSI 3 RESET 40 PC0 44 VCC 6 PB5 5 PB6 4 PB7 AD5/A5 28 39 AD15/A15 38 AD14/A14 37 AD13/A13 36 AD12/A12 35 AD11/A11 34 GND 33 AD10/A10 32 AD9/A9 31 AD8/A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 AD4/A4 27 (TOP VIEW) AD5/A5 28 2-115 PSD3XX Family 40 WR/VPP or R/W 39 BHE/PSEN 38 VCC 37 A19/CSI 41 RESET PSD303L Package Information 44 PB5 43 PB6 36 PC2 35 PC1 Figure 81. Drawing U1 - 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) 34 PC0 42 PB7 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 33 AD15/A15 32 AD14/A14 31 AD13/A13 30 AD12/A12 29 AD11/A11 28 GND 27 AD10/A10 26 AD9/A9 25 AD8/A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E/DS 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) 2-116 AD5/A5 22 Programmable Peripheral PSD313L 3-Volt Single-Chip Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 3.0 to 5.5 Volt Operation t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A & PAD B) -- Total of 40 Product Terms and up to 16 Inputs and 24 Outputs -- Direct Address Decoding up to 1 Meg address space and up to 16 Meg with paging -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode 8-bit data bus width ALE polarity programmable Selectable modes for read and write control bus as RD/WR, R/W/E, or R/W/DS PSEN pin for 8051 users t Built-In Page Logic -- To Expand the Address Space of Microcontrollers with Limited Address Space Capabilities -- Up to 16 pages t 1M bit of UV EPROM -- -- -- -- Configurable as 128K x 8 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 16K x 8 150 ns EPROM access time, including input latches and PAD address decoding. t 16 Kbit Static RAM -- Configurable as 2K x 8 -- 150 ns SRAM access time, including input latches and PAD address decoding t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t CMiser-Bit -- Programmable option to further reduce power consumption t Built-In Security -- Locks the PSD313L and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCC and TQFP t Simple Menu-Driven Software: Configure the PSD313L on an IBM PC t Pin and Functionally Compatible with the PSD3XX and PSD3XXL Series 2-117 PSD3XX Family PSD313L Pin Assignments Pin Name PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E/DS AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 A8 A9 A10 GND A11 A12 A13 A14 A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 2-118 PSD3XX Family 2 WR/VPP or R/W 43 A19/CSI 3 RESET PSD313L Package Information 6 PB5 5 PB6 1 PSEN 42 PC2 41 PC1 Figure 82. Drawing L4 -- 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 A15 38 A14 37 A13 36 A12 35 A11 34 GND 33 A10 32 A9 31 A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 42 PC2 AD4/A4 27 41 PC1 (TOP VIEW) Figure 83. Drawing J2 -- 44-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J) PB4 PB3 PB2 7 8 9 2 WR/VPP or R/W 43 A19/CSI 3 RESET 1 PSEN 40 PC0 44 VCC 6 PB5 5 PB6 4 PB7 AD5/A5 28 39 A15 38 A14 37 A13 36 A12 35 A11 34 GND 33 A10 32 A9 31 A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 AD4/A4 27 (TOP VIEW) AD5/A5 28 2-119 PSD3XX Family 40 WR/VPP or R/W 37 A19/CSI 41 RESET PSD313L Package Information 44 PB5 43 PB6 42 PB7 39 PSEN 36 PC2 35 PC1 Figure 84. Drawing U1 - 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) 34 PC0 38 VCC PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 33 A15 32 A14 31 A13 30 A12 29 A11 28 GND 27 A10 26 A9 25 A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E/DS 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) 2-120 AD5/A5 22 Programmable Peripheral PSD304RL 3-Volt Single-Chip Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 3.0 to 5.5 Volt Operation t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A & PAD B) -- Total of 40 Product Terms and up to 16 Inputs and 24 Outputs -- Direct Address Decoding up to 1 Meg address space and up to 16 Meg with paging -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode Selectable 8 or 16 bit data bus width ALE polarity programmable Selectable modes for read and write control bus as RD/WR, R/W/E, or R/W/DS BHE pin for byte select in 16-bit mode PSEN pin for 8051 users t Built-In Page Logic -- To Expand the Address Space of Microcontrollers with Limited Address Space Capabilities -- Up to 16 pages t 2M bit of UV EPROM -- -- -- -- Configurable as 256K x 8 or as 128K x 16 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 32K x 8 or 16K x 16 300 ns EPROM access time, including input latches and PAD address decoding. t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t CMiser-Bit -- Programmable option to further reduce power consumption t Built-In Security -- Locks the PSD304RL and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCC and TQFP t Simple Menu-Driven Software: Configure the PSD304RL on an IBM PC t Pin and Functionally Compatible with the PSD3XX and PSD3XXL Series 2-121 PSD3XX Family PSD304RL Pin Assignments Pin Name BHE/PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E/DS AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 AD8/A8 AD9/A9 AD10/A10 GND AD11/A11 AD12/A12 AD13/A13 AD14/A14 AD15/A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 2-122 PSD3XX Family 2 WR/VPP or R/W 1 BHE/PSEN 43 A19/CSI 3 RESET PSD304RL Package Information 6 PB5 5 PB6 42 PC2 41 PC1 Figure 85. Drawing L4 -- 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 AD15/A15 38 AD/14/A14 37 AD13/A13 36 AD12/A12 35 AD11/A11 34 GND 33 AD10/A10 32 AD9/A9 31 AD8/A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 42 PC2 AD4/A4 27 41 PC1 (TOP VIEW) Figure 86. Drawing J2 -- 44 Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J) PB4 PB3 PB2 7 8 9 2 WR/VPP or R/W 1 BHE/PSEN 43 A19/CSI 3 RESET 40 PC0 44 VCC 6 PB5 5 PB6 4 PB7 AD5/A5 28 39 AD15/A15 38 AD14/A14 37 AD13/A13 36 AD12/A12 35 AD11/A11 34 GND 33 AD10/A10 32 AD9/A9 31 AD8/A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 AD4/A4 27 (TOP VIEW) AD5/A5 28 2-123 PSD3XX Family 40 WR/VPP or R/W 39 BHE/PSEN 37 A19/CSI 41 RESET PSD304RL Package Information 44 PB5 43 PB6 42 PB7 36 PC2 35 PC1 Figure 87. Drawing U1 - 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) 34 PC0 38 VCC PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 33 AD15/A15 32 AD14/A14 31 AD13/A13 30 AD12/A12 29 AD11/A11 28 GND 27 AD10/A10 26 AD9/A9 25 AD8/A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E/DS 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) 2-124 AD5/A5 22 Programmable Peripheral PSD314RL 3-Volt Single-Chip Microcontroller Peripheral Key Features t Single Chip Programmable Peripheral for Microcontroller-based Applications t 3.0 to 5.5 Volt Operation t 19 Individually Configurable I/O pins that can be used as: -- -- -- -- Microcontroller I/O port expansion Programmable Address Decoder (PAD) I/O Latched address output Open drain or CMOS t Two Programmable Arrays (PAD A & PAD B) -- Total of 40 Product Terms and up to 16 Inputs and 24 Outputs -- Direct Address Decoding up to 1 Meg address space and up to 16 Meg with paging -- Logic replacement t "No Glue" Microcontroller Chip-Set -- -- -- -- -- -- Built-in address latches for multiplexed address/data bus Non-multiplexed address/data bus mode 8-bit data bus width ALE polarity programmable Selectable modes for read and write control bus as RD/WR, R/W/E, or R/W/DS PSEN pin for 8051 users t Built-In Page Logic -- To Expand the Address Space of Microcontrollers with Limited Address Space Capabilities -- Up to 16 pages t 2M bit of UV EPROM -- -- -- -- Configurable as 256K x 8 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 32K x 8 300 ns EPROM access time, including input latches and PAD address decoding. t Address/Data Track Mode -- Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor t CMiser-Bit -- Programmable option to further reduce power consumption t Built-In Security -- Locks the PSD314RL and PAD Decoding Configuration t Available in a Choice of Packages -- 44 Pin PLDCC, CLDCC and TQFP t Simple Menu-Driven Software: Configure the PSD314RL on an IBM PC t Pin and Functionally Compatible with the PSD3XX and PSD3XXL Series 2-125 PSD3XX Family PSD314RL Pin Assignments Pin Name PSEN WR/VPP or R/W RESET PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RD/E/DS AD0/A0 AD1/A1 AD2/A2 AD3/A3 AD4/A4 AD5/A5 AD6/A6 AD7/A7 A8 A9 A10 GND A11 A12 A13 A14 A15 PC0 PC1 PC2 A19/CSI VCC 44-Pin PLDCC/CLDCC Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-Pin TQFP Package 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 2-126 PSD3XX Family 2 WR/VPP or R/W 43 A19/CSI 3 RESET PSD314RL Package Information 6 PB5 5 PB6 1 PSEN 42 PC2 41 PC1 Figure 88. Drawing L4 -- 44 Pin Ceramic Leaded Chip Carrier (CLDCC) with Window (Package Type L) 40 PC0 44 VCC 4 PB7 PB4 PB3 PB2 7 8 9 39 A15 38 A14 37 A13 36 A12 35 A11 34 GND 33 A10 32 A9 31 A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 42 PC2 AD4/A4 27 41 PC1 (TOP VIEW) Figure 89. Drawing J2 -- 44-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J) PB4 PB3 PB2 7 8 9 2 WR/VPP or R/W 43 A19/CSI 3 RESET 1 PSEN 40 PC0 44 VCC 6 PB5 5 PB6 4 PB7 AD5/A5 28 39 A15 38 A14 37 A13 36 A12 35 A11 34 GND 33 A10 32 A9 31 A8 30 AD7/A7 29 AD6/A6 PB1 10 PB0 11 GND 12 ALE or AS 13 PA7 14 PA6 15 PA5 16 PA4 17 RD/E/DS 22 PA3 18 PA2 19 PA1 20 PA0 21 AD0/A0 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 AD4/A4 27 (TOP VIEW) AD5/A5 28 2-127 PSD3XX Family 40 WR/VPP or R/W 37 A19/CSI 41 RESET PSD314RL Package Information 44 PB5 43 PB6 42 PB7 39 PSEN 36 PC2 35 PC1 Figure 90. Drawing U1 - 44 Pin Plastic Thin Quad Flatpack (TQFP) (Package Type U) 34 PC0 38 VCC PB4 PB3 PB2 PB1 PB0 GND ALE or AS PA7 PA6 1 2 3 4 5 6 7 8 9 33 A15 32 A14 31 A13 30 A12 29 A11 28 GND 27 A10 26 A9 25 A8 24 AD7/A7 23 AD6/A6 PA5 10 PA4 11 PA3 12 PA2 13 PA1 14 PA0 15 RD/E/DS 16 AD0/A0 17 AD1/A1 18 AD2/A2 19 AD3/A3 20 AD4/A4 21 (TOP VIEW) PSD3XX Product Ordering Information PSD3XX family devices are available in a wide range of product selections. Options and combinations include: Architecture Speed (Access Time) Memory Size Configuration SRAM/no SRAM Mask Programmability Operating Temperature Range Supply Voltages Packages Please contact your local WSI Sales Representative or Distributor for the PSD3XX product selection that best fits your application and objectives. 2-128 AD5/A5 22 |
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